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1. 发明授权

US08115279B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08115279B2
公开(公告)日：2012-02-14
申请号：US12769271
申请日：2010-04-28
申请人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
发明人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
IPC分类号： H01L29/06
CPC分类号： H01L21/76264 , H01L21/743
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。扩散限制结构设置在隔离环结构的内部区域内。导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

2. 发明授权

US07749859B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07749859B2
公开(公告)日：2010-07-06
申请号：US11771583
申请日：2007-06-29
申请人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
发明人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
IPC分类号： H01L29/00
CPC分类号： H01L21/76264 , H01L21/743
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。扩散限制结构设置在隔离环结构的内部区域内。导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

3. 发明申请

US20100207238A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100207238A1
公开(公告)日：2010-08-19
申请号：US12769271
申请日：2010-04-28
申请人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
发明人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
IPC分类号： H01L29/06
CPC分类号： H01L21/76264 , H01L21/743
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。扩散限制结构设置在隔离环结构的内部区域内。导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

4. 发明申请

US20090001502A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090001502A1
公开(公告)日：2009-01-01
申请号：US11771583
申请日：2007-06-29
申请人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
发明人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L21/76264 , H01L21/743
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。扩散限制结构设置在隔离环结构的内部区域内。导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

5. 发明授权

US07534679B2 System and method for producing a semiconductor circuit arrangement 有权
标题翻译：用于制造半导体电路装置的系统和方法
公开(公告)号：US07534679B2
公开(公告)日：2009-05-19
申请号：US11586433
申请日：2006-10-25
申请人： Markus Rochel , Armin Tilke , Cajetan Wagner
发明人： Markus Rochel , Armin Tilke , Cajetan Wagner
IPC分类号： H01L21/8238
CPC分类号： H01L21/8249
摘要： Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed for the purpose of carrying out a first collector implantation for the purpose of forming a collector connection zone. After the formation of a hard mask layer and a first etching mask, the hard mask layer is patterned and an emitter window is uncovered using the patterned hard mask layer. Using the patterned hard mask layer a second collector implantation is effected for the purpose of forming a collector zone, a base layer being formed in the region of the emitter window. Afterward, using a second etching mask, a field effect transistor region is uncovered and the patterned hard mask layer is removed in this region in order finally to form a second electrically conductive layer over the whole area for the purpose of realizing an emitter layer and a second split gate layer. Both the bipolar transistor and the field effect transistor are subsequently completed in a customary manner, in particular a source/drain implantation being used simultaneously for the doping of the emitter layer. Since the gate is deposited in two layers, the first layer simultaneously serving as base connection layer and the second layer simultaneously serving as emitter layer, up to two lithography planes can be obviated and costs can thereby be saved.
摘要翻译：公开了用于制造半导体电路装置的方法和系统。在一个实施方案中，为了实现基极连接层和第一分离栅极层，在半导体衬底的表面上形成第一导电层之后，为了实现第一集电体而形成注入掩模用于形成集电器连接区域的植入。在形成硬掩模层和第一蚀刻掩模之后，使用图案化的硬掩模层对硬掩模层进行图案化并且发射窗未被覆盖。使用图案化的硬掩模层，进行第二集电极注入以形成集电区，在发射极窗的区域中形成基极层。之后，使用第二蚀刻掩模，不覆盖场效应晶体管区域，并且在该区域中去除图案化的硬掩模层，以便最终在整个区域上形成第二导电层，以实现发射极层和第二分裂门层。随后以常规方式完成双极晶体管和场效应晶体管，特别是与掺杂发射极层同时使用的源极/漏极注入。由于栅极沉积在两层中，所以可以避免同时用作基极连接层的第一层和同时用作发射极层的第二层，直到两个光刻平面，从而可以节省成本。

6. 发明申请

US20070224747A1 System and method for producing a semiconductor circuit arrangement 有权
标题翻译：用于制造半导体电路装置的系统和方法
公开(公告)号：US20070224747A1
公开(公告)日：2007-09-27
申请号：US11586433
申请日：2006-10-25
申请人： Markus Rochel , Armin Tilke , Cajetan Wagner
发明人： Markus Rochel , Armin Tilke , Cajetan Wagner
IPC分类号： H01L21/8234
CPC分类号： H01L21/8249
摘要： Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed for the purpose of carrying out a first collector implantation for the purpose of forming a collector connection zone. After the formation of a hard mask layer and a first etching mask, the hard mask layer is patterned and an emitter window is uncovered using the patterned hard mask layer. Using the patterned hard mask layer a second collector implantation is effected for the purpose of forming a collector zone, a base layer being formed in the region of the emitter window. Afterward, using a second etching mask, a field effect transistor region is uncovered and the patterned hard mask layer is removed in this region in order finally to form a second electrically conductive layer over the whole area for the purpose of realizing an emitter layer and a second split gate layer. Both the bipolar transistor and the field effect transistor are subsequently completed in a customary manner, in particular a source/drain implantation being used simultaneously for the doping of the emitter layer. Since the gate is deposited in two layers, the first layer simultaneously serving as base connection layer and the second layer simultaneously serving as emitter layer, up to two lithography planes can be obviated and costs can thereby be saved.
摘要翻译：公开了用于制造半导体电路装置的方法和系统。在一个实施方案中，为了实现基极连接层和第一分离栅极层，在半导体衬底的表面上形成第一导电层之后，为了实现第一集电体而形成注入掩模用于形成集电器连接区域的植入。在形成硬掩模层和第一蚀刻掩模之后，使用图案化的硬掩模层对硬掩模层进行图案化并且发射窗未被覆盖。使用图案化的硬掩模层，进行第二集电极注入以形成集电区，在发射极窗的区域中形成基极层。之后，使用第二蚀刻掩模，不覆盖场效应晶体管区域，并且在该区域中去除图案化的硬掩模层，以便最终在整个区域上形成第二导电层，以实现发射极层和第二分裂门层。随后以常规方式完成双极晶体管和场效应晶体管，特别是与掺杂发射极层同时使用的源极/漏极注入。由于栅极沉积在两层中，所以可以避免同时用作基极连接层的第一层和同时用作发射极层的第二层，直到两个光刻平面，从而可以节省成本。

7. 发明申请

US20050156193A1 Method for manufacturing an integrated circuit and integrated circuit with a bipolar transistor and a hetero bipolar transistor 有权
标题翻译：用于制造具有双极晶体管和异质双极晶体管的集成电路和集成电路的方法
公开(公告)号：US20050156193A1
公开(公告)日：2005-07-21
申请号：US10987952
申请日：2004-11-12
申请人： Claus Dahl , Karl-Heinz Mueller , Cajetan Wagner
发明人： Claus Dahl , Karl-Heinz Mueller , Cajetan Wagner
IPC分类号： H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L31/109
CPC分类号： H01L21/8249 , H01L21/8222 , H01L27/0623 , H01L27/0825
摘要： For the integration of an npn bipolar transistor with a hetero bipolar transistor, a placeholder layer is generated in a base region of the hetero bipolar transistor after structuring a collector structure for both types of transistors, wherein the placeholder layer is not present in a base region of the bipolar transistor. After generating the base of the bipolar transistor, the base of the bipolar transistor is covered, whereupon the placeholder layer is removed and the base of the hetero bipolar transistor is generated in the places where the placeholder layer has been removed. The emitter structure is again generated equally for both types of transistors so that an integrated circuit results which includes bipolar transistors and hetero bipolar transistors whose collector structures and/or whose emitter structures consist of identical production layers. Thus, space-saving and cost-effective integrated circuits may be produced benefiting from the advantages of both types of transistors.
摘要翻译：为了将npn双极晶体管与异质双极晶体管集成，在构造用于两种类型的晶体管的集电极结构之后，在异质双极晶体管的基极区域中产生占位符层，其中占位符层不存在于基极区域的双极晶体管。在产生双极晶体管的基极之后，双极晶体管的基极被覆盖，于是除去占位符层，并且在占位符层被去除的位置产生异质双极晶体管的基极。对于两种类型的晶体管，再次产生发射极结构，使得集成电路的结果包括双极晶体管和异质双极晶体管，其集电极结构和/或其发射极结构由相同的生产层组成。因此，可以利用两种类型的晶体管的优点来产生节省空间和成本有效的集成电路。

8. 发明授权

US07521733B2 Method for manufacturing an integrated circuit and integrated circuit with a bipolar transistor and a hetero bipolar transistor 有权
标题翻译：用于制造具有双极晶体管和异质双极晶体管的集成电路和集成电路的方法
公开(公告)号：US07521733B2
公开(公告)日：2009-04-21
申请号：US10987952
申请日：2004-11-12
申请人： Claus Dahl , Karl-Heinz Mueller , Cajetan Wagner
发明人： Claus Dahl , Karl-Heinz Mueller , Cajetan Wagner
IPC分类号： H01L29/737
CPC分类号： H01L21/8249 , H01L21/8222 , H01L27/0623 , H01L27/0825
摘要： For the integration of an npn bipolar transistor with a hetero bipolar transistor, a placeholder layer is generated in a base region of the hetero bipolar transistor after structuring a collector structure for both types of transistors, wherein the placeholder layer is not present in a base region of the bipolar transistor. After generating the base of the bipolar transistor, the base of the bipolar transistor is covered, whereupon the placeholder layer is removed and the base of the hetero bipolar transistor is generated in the places where the placeholder layer has been removed. The emitter structure is again generated equally for both types of transistors so that an integrated circuit results which includes bipolar transistors and hetero bipolar transistors whose collector structures and/or whose emitter structures consist of identical production layers. Thus, space-saving and cost-effective integrated circuits may be produced benefiting from the advantages of both types of transistors.
摘要翻译：为了将npn双极晶体管与异质双极晶体管集成，在构造用于两种类型的晶体管的集电极结构之后，在异质双极晶体管的基极区域中产生占位符层，其中占位符层不存在于基极区域的双极晶体管。在产生双极晶体管的基极之后，双极晶体管的基极被覆盖，于是除去占位符层，并且在占位符层被去除的位置产生异质双极晶体管的基极。对于两种类型的晶体管，再次产生发射极结构，使得集成电路的结果包括双极晶体管和异质双极晶体管，其集电极结构和/或其发射极结构由相同的生产层组成。因此，可以利用两种类型的晶体管的优点来产生节省空间和成本有效的集成电路。

9. 发明授权

US06852598B2 Method for the fabrication of a DMOS transistor 失效
标题翻译：制造DMOS晶体管的方法
公开(公告)号：US06852598B2
公开(公告)日：2005-02-08
申请号：US10424019
申请日：2003-04-25
申请人： Karlheinz Müller , Klaus Röschlau , Cajetan Wagner
发明人： Karlheinz Müller , Klaus Röschlau , Cajetan Wagner
IPC分类号： H01L29/78 , H01L21/336 , H01L29/423
CPC分类号： H01L29/66681 , H01L29/42368 , H01L29/66674 , H01L29/66689
摘要： A method for the fabrication of a DMOS transistor structure provides the advantage that, through the use of a protective layer, the DMOS transistor structure, which has already been substantially completed, is protected from the adverse effects of further process steps. The DMOS gate electrode is not, as is customary in the prior art, patterned using a single lithography step, but, rather, the patterning of the DMOS gate electrode is split between two lithography steps. In a first lithography step, substantially only the source region of the DMOS transistor structure is opened. Therefore, the electrode layer that is still present can be used as a mask for the subsequent fabrication of the body region.
摘要翻译：制造DMOS晶体管结构的方法提供的优点是，通过使用保护层，已经基本完成的DMOS晶体管结构被保护免受进一步处理步骤的不利影响。如现有技术中常规的DMOS栅极电极不是使用单个光刻步骤图案化的，而是DMOS栅电极的图案化在两个光刻步骤之间被分割。在第一光刻步骤中，基本上只有DMOS晶体管结构的源极区域被打开。因此，仍然存在的电极层可以用作随后制造身体区域的掩模。

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