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1. 发明申请

US20200035668A1 Devices and Methods to Control Clamping Devices 审中-公开
公开(公告)号：US20200035668A1
公开(公告)日：2020-01-30
申请号：US16044231
申请日：2018-07-24
申请人： Arm Limited , The Regents of the University of Michigan
发明人： Parameshwarappa Anand Kumar Savanth , Fabrice Blanc , David Theodore Blaauw , Sechang Oh , In Hee Lee
IPC分类号： H01L27/02 , H02H9/04 , H02H1/00
摘要： In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.

2. 发明授权

US11024624B2 Devices and methods to control clamping devices 有权
公开(公告)号：US11024624B2
公开(公告)日：2021-06-01
申请号：US16044231
申请日：2018-07-24
申请人： Arm Limited , The Regents of the University of Michigan
发明人： Parameshwarappa Anand Kumar Savanth , Fabrice Blanc , David Theodore Blaauw , Sechang Oh , In Hee Lee
IPC分类号： H01L27/02 , H02H1/00 , H02H9/04
摘要： In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.

3. 发明申请

US20220393462A1 Circuits to Control a Clamping Device 有权
公开(公告)号：US20220393462A1
公开(公告)日：2022-12-08
申请号：US17406855
申请日：2021-08-19
申请人： Arm Limited
发明人： Seshagiri Rao Bogi , Gurupadayya Shidaganti , Fabrice Blanc
IPC分类号： H02H9/04 , H01L27/02 , H01L23/60
摘要： In a particular implementation, an apparatus to control clamping devices includes a detection circuitry, a clamping device, inverter circuitry, and first and second control circuitry. In response to a first voltage corresponding to a gate terminal of the clamping device, the first control circuitry is configured to generate a second voltage to set the first voltage below a first voltage threshold. Also, in response to the second voltage, the second control circuitry is configured to generate a third voltage to set a voltage of the detection circuitry below a second voltage threshold.

4. 发明授权

US11495955B2 Rectifier triggering techniques 有权
公开(公告)号：US11495955B2
公开(公告)日：2022-11-08
申请号：US16785513
申请日：2020-02-07
申请人： Arm Limited
发明人： Seshagiri Rao Bogi , Fabrice Blanc
IPC分类号： H02H9/02 , H02H1/00 , H01L27/02 , H02H9/04 , H05K13/00
摘要： Various implementations described herein are related to a device having switching circuitry that provides a rectified voltage when triggered. The device may include diode circuitry coupled in series with charge storage circuitry. The diode circuitry and the charge storage circuitry may operate to trigger the switching circuitry. The diode circuitry may include one or more diodes, and the charge storage circuitry may include at least one charge storage component.

5. 发明申请

US20150371686A1 Read Assist Techniques in a Memory Device 有权
标题翻译：在内存设备中阅读辅助技术
公开(公告)号：US20150371686A1
公开(公告)日：2015-12-24
申请号：US14745355
申请日：2015-06-19
申请人： ARM Limited
发明人： Nicolaas Van Winkelhoff , Mikael Brun , Fabrice Blanc
IPC分类号： G11C7/00
CPC分类号： G11C11/418 , G11C5/14 , G11C7/00 , G11C8/08 , G11C8/10
摘要： A memory device is provided which comprises an array of bitcells and a plurality of wordlines. Each bitcell of the array of bitcells is selectively coupled to a wordline of the plurality of wordlines and access to a selected bitcell of the array of bitcells requires an asserted voltage on a selected wordline with which the selected bitcell is associated. Read assist circuitry is provided, which is configured, when read access to the selected bitcell is carried out, to implement a reduction in the asserted voltage on the selected wordline, and wherein the read assist circuitry is configured to implement the reduction in the asserted voltage by selective connection of the selected wordline to a further wordline of the plurality of wordlines.
摘要翻译：提供了一种存储器件，其包括位单元阵列和多个字线。位单元阵列的每个比特单元被选择性地耦合到多个字线的字线，并且访问位单元阵列的所选位单元需要与所选位单元相关联的所选字线上的有效电压。提供了读辅助电路，其被配置为当执行对所选择的位单元的读取访问时，实现所选择的字线上的被断言的电压的降低，并且其中所述读辅助电路被配置为实现所述被确定的电压的减小通过选择性地连接所选择的字线到多个字线的另一个字线。

6. 发明申请

US20210249849A1 Rectifier Triggering Techniques 有权
公开(公告)号：US20210249849A1
公开(公告)日：2021-08-12
申请号：US16785513
申请日：2020-02-07
申请人： Arm Limited
发明人： Seshagiri Rao Bogi , Fabrice Blanc
IPC分类号： H02H1/00 , H02H9/02
摘要： Various implementations described herein are related to a device having switching circuitry that provides a rectified voltage when triggered. The device may include diode circuitry coupled in series with charge storage circuitry. The diode circuitry and the charge storage circuitry may operate to trigger the switching circuitry. The diode circuitry may include one or more diodes, and the charge storage circuitry may include at least one charge storage component.

7. 发明申请

US20160172350A1 Electrostatic Discharge Protection Circuitry 有权
标题翻译：静电放电保护电路
公开(公告)号：US20160172350A1
公开(公告)日：2016-06-16
申请号：US14570142
申请日：2014-12-15
申请人： ARM Limited
发明人： Ranabir Dey , Abhinav Kumar , Vijaya Kumar Vinukonda , Fabrice Blanc
IPC分类号： H01L27/02 , H02H9/04 , H01L29/78
CPC分类号： H02H9/046 , H01L27/0285 , H01L29/78
摘要： Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.
摘要翻译：本文描述的各种实现涉及用于静电放电（ESD）保护的集成电路。集成电路可以包括具有电阻器和与第二电容器级联的第一电容器的检测级。电阻器和第一电容器被布置成限定被配置为提供触发信号的触发节点。布置第一电容器和第二电容器以限定被配置为提供参考信号的参考节点。集成电路可以包括第一ESD钳位级，其具有被配置为基于触发信号向第一钳位晶体管提供电源电压的第一晶体管。集成电路可以包括第二ESD钳位级，其具有被配置为从第一晶体管接收电源电压并且基于参考信号将电源电压提供给第二钳位晶体管的第二晶体管。

8. 发明申请

US20160322806A1 Power Supply Clamp 审中-公开
标题翻译：电源钳
公开(公告)号：US20160322806A1
公开(公告)日：2016-11-03
申请号：US15130920
申请日：2016-04-15
申请人： ARM Limited
发明人： Abdellah Bakhali , Mikael Rien , Fabrice Blanc
IPC分类号： H02H3/20 , G01R31/40 , G01R29/08
CPC分类号： H02H3/20 , G01R29/0814 , G01R31/40 , G01R31/44 , H02H9/041 , H02H9/046
摘要： A power supply clamp connectable between power rails of an electronic circuit comprises a switching component which is switchable to provide a connection path between the power rails of the electronic circuit; a first detector configured to detect an electrostatic discharge event having a first characteristic time period and to generate a detector output signal in response to the detection; a series of one or more successive intermediate amplification stages between the first detector and the switching component, the series of amplification stages providing a control signal path for a control signal to control switching of the switching component in response to the detector output signal; and a second detector configured to detect an electrostatic discharge event having a second characteristic time period, shorter than the first characteristic time period, the second detector being provided at a node in the control signal path subsequent to the first detector (for example, at a second or subsequent one of the series of intermediate amplification stages) so that a detection by the second detector causes the control signal to control switching of the switching component.
摘要翻译：可连接在电子电路的电源轨道之间的电源钳包括切换部件，该切换部件可切换以提供电子电路的电源轨之间的连接路径; 第一检测器，被配置为检测具有第一特征时间段的静电放电事件，并响应于所述检测而产生检测器输出信号; 在第一检测器和开关部件之间的一系列一个或多个连续的中间放大级，所述一系列放大级提供用于控制信号的控制信号路径，以响应于检测器输出信号来控制开关部件的切换; 以及第二检测器，被配置为检测具有比所述第一特征时间段短的第二特征时间段的静电放电事件，所述第二检测器设置在所述第一检测器之后的控制信号路径中的节点处（例如，第二或后续的一系列中间放大级），使得第二检测器的检测使控制信号控制开关元件的开关。

9. 发明授权

US11621555B2 Circuits to control a clamping device 有权
公开(公告)号：US11621555B2
公开(公告)日：2023-04-04
申请号：US17406855
申请日：2021-08-19
申请人： Arm Limited
发明人： Seshagiri Rao Bogi , Gurupadayya Shidaganti , Fabrice Blanc
IPC分类号： H02H9/04 , H01L23/60 , H01L27/02
摘要： In a particular implementation, an apparatus to control clamping devices includes a detection circuitry, a clamping device, inverter circuitry, and first and second control circuitry. In response to a first voltage corresponding to a gate terminal of the clamping device, the first control circuitry is configured to generate a second voltage to set the first voltage below a first voltage threshold. Also, in response to the second voltage, the second control circuitry is configured to generate a third voltage to set a voltage of the detection circuitry below a second voltage threshold.

10. 发明申请

US20220038101A1 LEVEL DOWN SHIFTER 有权
公开(公告)号：US20220038101A1
公开(公告)日：2022-02-03
申请号：US17021393
申请日：2020-09-15
申请人： Arm Limited
发明人： Seshagiri Rao Bogi , Gayathri Gandhi , Vinay Chenani , Fabrice Blanc
IPC分类号： H03K19/0185 , H03K19/17784 , H03K3/356
摘要： A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain.

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