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1. 发明申请

US20140003441A1 Responding to dynamically-connected transport requests 有权
公开(公告)号：US20140003441A1
公开(公告)日：2014-01-02
申请号：US13535382
申请日：2012-06-28
申请人： Ariel Shachar , Michael Kagan , Noam Bloch
发明人： Ariel Shachar , Michael Kagan , Noam Bloch
IPC分类号： H04L12/56
CPC分类号： H04L5/0055 , H04L47/10
摘要： A method for communication, includes allocating, in a network interface controller (NIC) a single dynamically-connected (DC) initiator context for serving requests from an initiator process running on the initiator host to transmit data to multiple target processes running on one or more target nodes. The NIC transmits a first connect packet directed to a first target process and referencing the DC initiator context so as to open a first dynamic connection with the first target process. The NIC receives over the packet network, in response to the first connect packet, a first acknowledgment packet containing a first session identifier (ID). Following receipt of the first acknowledgment packet, the NIC transmits one or more first data packets containing the first session ID over the first dynamic connection from the NIC to the first target process. Dynamic connections with other target processes may subsequently be handled in similar fashion.

2. 发明授权

US08225182B2 Processing of block and transaction signatures 有权
标题翻译：块和交易签名的处理
公开(公告)号：US08225182B2
公开(公告)日：2012-07-17
申请号：US12573119
申请日：2009-10-04
申请人： Michael Kagan , Noam Bloch , Ariel Shachar
发明人： Michael Kagan , Noam Bloch , Ariel Shachar
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H04L67/1097 , H04L63/123
摘要： A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.
摘要翻译：网络通信设备包括主机接口，其被耦合以与主机处理器通信，具有主机存储器，以便接收工作请求以执行要通过分组网络传送多个数据块的事务。处理电路被配置为处理多个数据分组以执行事务，事务中的每个数据分组包含一部分数据块，并且多个数据分组至少包括第一和最后一个分组，其分别包含第一和最后一个分组数据块的交易。处理电路被配置为在处理数据分组时计算数据块上的事务签名，使得至少第一数据块在完成交易签名的计算之前通过其中一个接口通过网络通信设备。

3. 发明申请

US20120246535A1 PROCESSING OF BLOCK AND TRANSACTION SIGNATURES 有权
标题翻译：块和交易签名的处理
公开(公告)号：US20120246535A1
公开(公告)日：2012-09-27
申请号：US13489474
申请日：2012-06-06
申请人： Michael Kagan , Noam Bloch , Ariel Shachar
发明人： Michael Kagan , Noam Bloch , Ariel Shachar
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L67/1097 , H04L63/123
摘要： A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.
摘要翻译：网络通信设备包括主机接口，其被耦合以与主机处理器通信，具有主机存储器，以便接收工作请求以执行要通过分组网络传送多个数据块的事务。处理电路被配置为处理多个数据分组以执行事务，事务中的每个数据分组包含一部分数据块，并且多个数据分组至少包括第一和最后一个分组，其分别包含第一和最后一个分组数据块的交易。处理电路被配置为在处理数据分组时计算数据块上的事务签名，使得至少第一数据块在完成交易签名的计算之前通过其中一个接口通过网络通信设备。

4. 发明申请

US20110083064A1 PROCESSING OF BLOCK AND TRANSACTION SIGNATURES 有权
标题翻译：块和交易签名的处理
公开(公告)号：US20110083064A1
公开(公告)日：2011-04-07
申请号：US12573119
申请日：2009-10-04
申请人： Michael Kagan , Noam Bloch , Ariel Shachar
发明人： Michael Kagan , Noam Bloch , Ariel Shachar
IPC分类号： G06F11/07 , G06F15/16
CPC分类号： H04L67/1097 , H04L63/123
摘要： A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.
摘要翻译：网络通信设备包括主机接口，其被耦合以与主机处理器通信，具有主机存储器，以便接收工作请求以执行要通过分组网络传送多个数据块的事务。处理电路被配置为处理多个数据分组以执行事务，事务中的每个数据分组包含一部分数据块，并且多个数据分组至少包括第一和最后一个分组，其分别包含第一和最后一个分组数据块的交易。处理电路被配置为在处理数据分组时计算数据块上的事务签名，使得至少第一数据块在完成交易签名的计算之前通过其中一个接口通过网络通信设备。

5. 发明授权

US08761189B2 Responding to dynamically-connected transport requests 有权
标题翻译：响应动态连接的传输请求
公开(公告)号：US08761189B2
公开(公告)日：2014-06-24
申请号：US13535382
申请日：2012-06-28
申请人： Ariel Shachar , Michael Kagan , Noam Bloch
发明人： Ariel Shachar , Michael Kagan , Noam Bloch
IPC分类号： H04L12/12
CPC分类号： H04L5/0055 , H04L47/10
摘要： A method for communication, includes allocating, in a network interface controller (NIC) a single dynamically-connected (DC) initiator context for serving requests from an initiator process running on the initiator host to transmit data to multiple target processes running on one or more target nodes. The NIC transmits a first connect packet directed to a first target process and referencing the DC initiator context so as to open a first dynamic connection with the first target process. The NIC receives over the packet network, in response to the first connect packet, a first acknowledgment packet containing a first session identifier (ID). Following receipt of the first acknowledgment packet, the NIC transmits one or more first data packets containing the first session ID over the first dynamic connection from the NIC to the first target process. Dynamic connections with other target processes may subsequently be handled in similar fashion.
摘要翻译：一种用于通信的方法，包括在网络接口控制器（NIC）中分配单个动态连接（DC）发起者上下文，用于从在所述发起者主机上运行的发起者进程提供请求以将数据发送到在一个或多个上运行的多个目标进程目标节点。 NIC发送指向第一目标进程的第一连接分组并引用DC启动器上下文以便打开与第一目标进程的第一动态连接。响应于第一连接分组，NIC通过分组网络接收包含第一会话标识符（ID）的第一确认分组。在接收到第一确认分组之后，NIC通过第一动态连接从NIC传送包含第一会话ID的第一数据分组到第一目标进程。与其他目标进程的动态连接可以随后以类似的方式来处理。

6. 发明授权

US08751909B2 Processing of block and transaction signatures 有权
标题翻译：块和交易签名的处理
公开(公告)号：US08751909B2
公开(公告)日：2014-06-10
申请号：US13489474
申请日：2012-06-06
申请人： Michael Kagan , Noam Bloch , Ariel Shachar
发明人： Michael Kagan , Noam Bloch , Ariel Shachar
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H04L67/1097 , H04L63/123
摘要： A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.
摘要翻译：网络通信设备包括主机接口，其被耦合以与主机处理器通信，具有主机存储器，以便接收工作请求以执行要通过分组网络传送多个数据块的事务。处理电路被配置为处理多个数据分组以执行事务，事务中的每个数据分组包含一部分数据块，并且多个数据分组至少包括第一和最后一个分组，其分别包含第一和最后一个分组数据块的交易。处理电路被配置为在处理数据分组时计算数据块上的事务签名，使得至少第一数据块在完成交易签名的计算之前通过其中一个接口通过网络通信设备。

7. 发明授权

US08811417B2 Cross-channel network operation offloading for collective operations 有权
标题翻译：跨渠道网络运营卸载集体运营
公开(公告)号：US08811417B2
公开(公告)日：2014-08-19
申请号：US12945904
申请日：2010-11-15
申请人： Noam Bloch , Gil Bloch , Ariel Shachar , Hillel Chapman , Ishai Rabinovitz , Pavel Shamis , Gilad Shainer
发明人： Noam Bloch , Gil Bloch , Ariel Shachar , Hillel Chapman , Ishai Rabinovitz , Pavel Shamis , Gilad Shainer
IPC分类号： H04L12/28 , H04L12/56 , G06F9/54
CPC分类号： H04L67/10 , G06F9/546 , G06F2209/509
摘要： A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.
摘要翻译：网络接口（NI）包括主机接口，其被配置为从节点的主机处理器接收从要由节点执行的操作导出的一个或多个跨通道工作请求。 NI包括用于通过网络向一个或多个对等节点执行传输信道的多个工作队列。 NI还包括控制电路，其被配置为经由主机接口接受跨通道工作请求，并且通过根据一个或多个控制电路控制至少一个给定的工作队列的前进来执行使用工作队列的跨通道工作请求这取决于一个或多个其他工作队列的完成状态，以便执行操作。

8. 发明申请

US20110119673A1 CROSS-CHANNEL NETWORK OPERATION OFFLOADING FOR COLLECTIVE OPERATIONS 有权
标题翻译：跨渠道网络操作卸载集合操作
公开(公告)号：US20110119673A1
公开(公告)日：2011-05-19
申请号：US12945904
申请日：2010-11-15
申请人： Noam Bloch , Gil Bloch , Ariel Shachar , Hillel Chapman , Ishai Rabinobitz , Pavel Shamis , Gilad Shainer
发明人： Noam Bloch , Gil Bloch , Ariel Shachar , Hillel Chapman , Ishai Rabinobitz , Pavel Shamis , Gilad Shainer
IPC分类号： G06F13/14 , G06F9/46
CPC分类号： H04L67/10 , G06F9/546 , G06F2209/509
摘要： A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.
摘要翻译：网络接口（NI）包括主机接口，其被配置为从节点的主机处理器接收从要由节点执行的操作导出的一个或多个跨通道工作请求。 NI包括用于通过网络向一个或多个对等节点执行传输信道的多个工作队列。 NI还包括控制电路，其被配置为经由主机接口接受跨通道工作请求，并且通过根据一个或多个控制电路控制至少一个给定的工作队列的前进来执行使用工作队列的跨通道工作请求这取决于一个或多个其他工作队列的完成状态，以便执行操作。

9. 发明授权

US08645663B2 Network interface controller with flexible memory handling 有权
标题翻译：网络接口控制器，灵活的内存处理
公开(公告)号：US08645663B2
公开(公告)日：2014-02-04
申请号：US13229772
申请日：2011-09-12
申请人： Michael Kagan , Ariel Shahar , Noam Bloch
发明人： Michael Kagan , Ariel Shahar , Noam Bloch
IPC分类号： G06F12/00
CPC分类号： G06F12/1081
摘要： An input/output (I/O) device includes a host interface for connection to a host device having a memory, and a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Processing circuitry is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory. At least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges.
摘要翻译：输入/输出（I / O）设备包括用于连接到具有存储器的主机设备的主机接口和网络接口，其被配置为通过网络发送和接收与指向的I / O操作相关联的数据分组到内存中指定的虚拟地址。处理电路被配置为使用结合I / O操作提供的存储器键将虚拟地址转换成物理地址，并且通过访问存储器中的物理地址来执行I / O操作。存储键中的至少一个是间接存储器密钥，其指向对应于虚拟地址的多个相应范围的多个直接存储器密钥，使得引用间接存储器密钥的I / O操作可以使处理电路访问在多个相应范围中的至少两个中的存储器。

10. 发明申请

US20130067193A1 NETWORK INTERFACE CONTROLLER WITH FLEXIBLE MEMORY HANDLING 有权
标题翻译：具有灵活存储器处理的网络接口控制器
公开(公告)号：US20130067193A1
公开(公告)日：2013-03-14
申请号：US13229772
申请日：2011-09-12
申请人： Michael Kagan , Ariel Shahar , Noam Bloch
发明人： Michael Kagan , Ariel Shahar , Noam Bloch
IPC分类号： G06F12/10
CPC分类号： G06F12/1081
摘要： An input/output (I/O) device includes a host interface for connection to a host device having a memory, and a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Processing circuitry is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory. At least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges.
摘要翻译：输入/输出（I / O）设备包括用于连接到具有存储器的主机设备的主机接口和网络接口，其被配置为通过网络发送和接收与指向的I / O操作相关联的数据分组到内存中指定的虚拟地址。处理电路被配置为使用结合I / O操作提供的存储器键将虚拟地址转换成物理地址，并且通过访问存储器中的物理地址来执行I / O操作。存储键中的至少一个是间接存储器密钥，其指向对应于虚拟地址的多个相应范围的多个直接存储器密钥，使得引用间接存储器密钥的I / O操作可以使处理电路访问在多个相应范围中的至少两个中的存储器。

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