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1. 发明授权

US5825318A Data and servo sampling in synchronous data detection channel 失效
标题翻译：数据和伺服采样同步数据检测通道
公开(公告)号：US5825318A
公开(公告)日：1998-10-20
申请号：US769823
申请日：1996-12-19
申请人： Ara Patapoutian , Kevin D. Fisher , Bruce D. Buch
发明人： Ara Patapoutian , Kevin D. Fisher , Bruce D. Buch
IPC分类号： G11B5/55 , G11B5/596 , G11B20/10 , G11B20/12 , G11B21/08 , G11B21/10 , H03M1/20 , H03M1/48
CPC分类号： G11B5/59605 , G11B20/10009 , G11B21/085 , G11B21/106 , G11B5/5547 , G11B5/59655 , H03M1/201 , G11B20/1258
摘要： An analog-to-digital converter circuit in a sampling data detection channel of a disk drive synchronously samples user data in the data track areas at a first quantization resolution and samples servo bursts from the spoke areas at a second quantization resolution effectively greater than said first quantization resolution. An offset circuit provides a predetermined analog offset signal to a combining circuit which combines it with an incoming analog signal to provide a composite signal during a spoke servo burst sampling interval. An analog-to-digital converter samples the composite signal during the servo spoke burst sampling interval, and synchronously samples the analog signal during a user data sampling interval. A digital averaging circuit averages the servo spoke samples over a predetermined averaging interval to provide averaged burst samples having increased bit resolution.
摘要翻译：磁盘驱动器的采样数据检测通道中的模拟 - 数字转换器电路以第一量化分辨率同步采样数据轨道区域中的用户数据，并且以比第二量化分辨率有效地大的第二量化分辨率从轮辐区域采样伺服脉冲串量化分辨率。偏移电路向组合电路提供预定的模拟偏移信号，该组合电路将其与输入模拟信号组合，以在辐射伺服脉冲串采样间隔期间提供复合信号。模数转换器在伺服轮询突发采样间隔期间对复合信号进行采样，并在用户数据采样间隔期间同步采样模拟信号。数字平均电路在预定的平均间隔上对伺服轮辐样本进行平均，以提供具有增加的比特分辨率的平均突发样本。

2. 发明授权

US08627175B2 Opportunistic decoding in memory systems 有权
标题翻译：内存系统中的机会解码
公开(公告)号：US08627175B2
公开(公告)日：2014-01-07
申请号：US12891490
申请日：2010-09-27
申请人： Ara Patapoutian , Bernardo Rub , Bruce D. Buch
发明人： Ara Patapoutian , Bernardo Rub , Bruce D. Buch
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F11/1048 , G11C16/26 , G11C29/844 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/45 , H03M13/451 , H03M13/458
摘要： Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.
摘要翻译：用于解码从非易失性固态存储器的存储器单元读取的数据的方法包括在软数据可用于解码器的时间之前尝试使用硬解码处理对硬数据进行解码。硬数据包括关于存储在存储器单元中的数字符号的信息，而没有数据置信度信息。软数据包括关于存储在存储单元中的数字符号和数据置信度的信息。响应于难以实现收敛的硬解码处理，在软数据变得可用于解码器之后，使用软解码处理解码软数据。在硬解码处理或软解码处理实现收敛之后，解码器生成解码数据的输出。

3. 发明申请

US20110296272A1 OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES 有权
标题翻译：固态存储器件的外部代码保护
公开(公告)号：US20110296272A1
公开(公告)日：2011-12-01
申请号：US12790120
申请日：2010-05-28
申请人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
发明人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/1012
摘要： Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.
摘要翻译：外码字可以跨越存储器设备的多个数据块，多个芯片或多个芯片，以防止存储在块，芯片和/或芯片中的数据中的错误。固态存储器件被布置在多个数据块中，每个块包括以多页布置的存储器单元的阵列。数据被编码成内码字和基于符号的外码字。内码字和基于符号的外码字被存储在多个块的存储单元中。一个或多个内部码字被存储在每个块的每个页面中，并且每个外部码字的一个或多个符号被存储在每个块的至少一个页面中。内部码字和外部码字从存储器件读取并用于校正数据中的错误。

4. 发明授权

US09015549B2 Iterating inner and outer codes for data recovery 有权
标题翻译：迭代内部和外部代码进行数据恢复
公开(公告)号：US09015549B2
公开(公告)日：2015-04-21
申请号：US13094048
申请日：2011-04-26
申请人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
发明人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
IPC分类号： H03M13/00 , G11B20/18 , H03M13/29 , H03M13/37 , H03M13/11 , H03M13/15
CPC分类号： G11B20/1833 , G11B2020/1836 , G11B2020/1853 , G11B2220/2516 , H03M13/1102 , H03M13/1515 , H03M13/2909 , H03M13/2927 , H03M13/3746
摘要： A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable.
摘要翻译：存储介质包括定义多个基于符号的内码字和多个基于符号的外码字的至少一个数据单元。包含在其中一个内部码字中的每个符号也被包括在一个外部码字中。处理器被配置为对所述多个基于符号的内码字执行内码纠错的第一迭代，对所述多个基于符号的外码字进行外码纠错的第一迭代和内码的第二次迭代对多个基于符号的内码字进行纠错。在外码错误校正的第一次迭代中，外码字中的至少一个是可校正的。在内码纠错的第二次迭代中，内码字中的至少一个是可校正的。

5. 发明授权

US08130553B2 Systems and methods for low wear operation of solid state memory 有权
标题翻译：固态存储器低磨损运行的系统和方法
公开(公告)号：US08130553B2
公开(公告)日：2012-03-06
申请号：US12629481
申请日：2009-12-02
申请人： Bruce D. Buch , Ara Patapoutian , Bengt A. Ulriksson , Bernardo Rub
发明人： Bruce D. Buch , Ara Patapoutian , Bengt A. Ulriksson , Bernardo Rub
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/349
摘要： This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.
摘要翻译：本公开涉及固态存储器（例如闪速存储器）的低磨损操作的系统和方法。在一个示例中，控制器耦合到存储器并且适于在数据存储设备的使用过程中动态地调整编程阈值，使得从存储在数据存储单元中的读取数据的信噪比不小于使用增强的错误检测功能恢复数据所需的最小数量。

6. 发明授权

US08572457B2 Outer code protection for solid state memory devices 有权
标题翻译：固态存储器件的外部代码保护
公开(公告)号：US08572457B2
公开(公告)日：2013-10-29
申请号：US12790120
申请日：2010-05-28
申请人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
发明人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
IPC分类号： H03M13/00 , G11C29/00 , G06F11/00
CPC分类号： G06F11/1012
摘要： Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.
摘要翻译：外码字可以跨越存储器设备的多个数据块，多个芯片或多个芯片，以防止存储在块，芯片和/或芯片中的数据中的错误。固态存储器件被布置在多个数据块中，每个块包括以多页布置的存储器单元的阵列。数据被编码成内码字和基于符号的外码字。内码字和基于符号的外码字被存储在多个块的存储单元中。一个或多个内部码字被存储在每个块的每个页面中，并且每个外部码字的一个或多个符号被存储在每个块的至少一个页面中。内部码字和外部码字从存储器件读取并用于校正数据中的错误。

7. 发明申请

US20120278679A1 Iterating Inner and Outer Codes for Data Recovery 有权
标题翻译：迭代内部和外部代码进行数据恢复
公开(公告)号：US20120278679A1
公开(公告)日：2012-11-01
申请号：US13094048
申请日：2011-04-26
申请人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
发明人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11B20/1833 , G11B2020/1836 , G11B2020/1853 , G11B2220/2516 , H03M13/1102 , H03M13/1515 , H03M13/2909 , H03M13/2927 , H03M13/3746
摘要： A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable.
摘要翻译：存储介质包括定义多个基于符号的内码字和多个基于符号的外码字的至少一个数据单元。包含在其中一个内部码字中的每个符号也被包括在一个外部码字中。处理器被配置为对所述多个基于符号的内码字执行内码纠错的第一迭代，对所述多个基于符号的外码字进行外码纠错的第一迭代和内码的第二次迭代对多个基于符号的内码字进行纠错。在外码错误校正的第一次迭代中，外码字中的至少一个是可校正的。在内码纠错的第二次迭代中，内码字中的至少一个是可校正的。

8. 发明授权

US08243511B2 Reuse of information from memory read operations 有权
标题翻译：从内存读取操作重新使用信息
公开(公告)号：US08243511B2
公开(公告)日：2012-08-14
申请号：US12891475
申请日：2010-09-27
申请人： Ara Patapoutian , Bernardo Rub , Bruce D. Buch
发明人： Ara Patapoutian , Bernardo Rub , Bruce D. Buch
IPC分类号： G11C16/08 , G11C16/28
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/3418
摘要： A nominal reference read operation compares analog voltages of the memory cells to at least one nominal reference voltage. A shifted reference read operation compares the analog voltages of the memory cells to at least one shifted reference voltage that is shifted from the nominal reference voltage to compensate for an expected change in the analog voltages of the memory cells. Data stored in the memory cells is decoded by a first decoding process that uses the information from either the nominal reference read operation or the shifted reference read operation. The data stored in the memory cells is decoded by a second decoding process that uses the information from both the nominal reference read operation and the shifted reference read operation.
摘要翻译：标称参考读取操作将存储器单元的模拟电压与至少一个标称参考电压进行比较。移位的参考读取操作将存储器单元的模拟电压与从标称参考电压偏移的至少一个移位的参考电压进行比较，以补偿存储器单元的模拟电压的预期变化。通过使用来自标称参考读取操作或移位参考读取操作的信息的第一解码处理对存储单元中存储的数据进行解码。通过使用来自标称参考读取操作和偏移的参考读取操作的信息的第二解码处理来对存储单元中存储的数据进行解码。

9. 发明申请

US20110131444A1 SYSTEMS AND METHODS FOR LOW WEAR OPERATION OF SOLID STATE MEMORY 有权
标题翻译：固态存储器低磨损运行的系统和方法
公开(公告)号：US20110131444A1
公开(公告)日：2011-06-02
申请号：US12629481
申请日：2009-12-02
申请人： Bruce D. Buch , Ara Patapoutian , Bengt A. Ulriksson , Bernardo Rub
发明人： Bruce D. Buch , Ara Patapoutian , Bengt A. Ulriksson , Bernardo Rub
IPC分类号： G11C16/14 , G11C16/10 , G11C16/04 , G06F11/20 , G06F11/00
CPC分类号： G11C16/10 , G11C16/349
摘要： This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.
摘要翻译：本公开涉及固态存储器（例如闪速存储器）的低磨损操作的系统和方法。在一个示例中，控制器耦合到存储器并且适于在数据存储设备的使用过程中动态地调整编程阈值，使得从存储在数据存储单元中的读取数据的信噪比不小于使用增强的错误检测功能恢复数据所需的最小数量。

10. 发明授权

US08254167B2 Joint encoding of logical pages in multi-page memory architecture 有权
标题翻译：在多页内存架构中对逻辑页进行联合编码
公开(公告)号：US08254167B2
公开(公告)日：2012-08-28
申请号：US12781774
申请日：2010-05-17
申请人： Ara Patapoutian , Deepak Sridhara , Bruce D. Buch
发明人： Ara Patapoutian , Deepak Sridhara , Bruce D. Buch
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C29/00 , G11C2216/14
摘要： Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.
摘要翻译：多个逻辑页面被联合编码成单个码字，并被存储在具有多层存储器单元的固态非易失性存储器（NVM）设备的相同物理页面中。多个逻辑页面的第一逻辑页面被存储在存储器设备中作为多级存储器单元的第一位，而多个逻辑页面的第二逻辑页面被临时高速缓存。在将第一逻辑页面存储为存储器单元的第一位之后，第二逻辑页面被存储为存储器单元的第二位。

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