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1. 发明授权

US09762999B1 Modal based architecture for controlling the directivity of loudspeaker arrays 有权
公开(公告)号：US09762999B1
公开(公告)日：2017-09-12
申请号：US14869760
申请日：2015-09-29
申请人： Apple Inc.
发明人： Martin E. Johnson , Gordon R. Dix , Vijay G. Prabakaran , Tom-Davy William Jendrik Saux
IPC分类号： H04R5/00 , H04R1/40
CPC分类号： H04R1/403 , H04R3/12 , H04R5/02 , H04R2201/40 , H04R2201/401
摘要： A directivity pattern generator for producing sound patterns using a modal architecture is described. The directivity pattern generator may include a beam pattern mixing unit, which defines sound patterns to be emitted by an audio system in terms of a set of frequency invariant modes or modal patterns. The beam pattern mixing unit produces a set of modal gains representing the level or degree each of the predefined modal patterns is to be applied to a set of audio streams. Modal filters may be used to modal amplitudes that compensate for inefficiencies of the each modal pattern at low frequencies. The directivity pattern generator may include a modal decomposition unit for generating driving signals for each transducer in one or more loudspeaker arrays based on weighted values for the modal gains/amplitudes.

2. 发明授权

US09007386B2 Clock synthesis 有权
标题翻译：时钟综合
公开(公告)号：US09007386B2
公开(公告)日：2015-04-14
申请号：US13708855
申请日：2012-12-07
申请人： Apple Inc.
发明人： Vijay G. Prabakaran
IPC分类号： G09G5/36 , G09G5/00
CPC分类号： G09G5/008 , G09G2310/08 , G09G2360/121
摘要： One embodiment of a clock synthesis apparatus can include a clock generator that can provide two or more clock waveforms. One clock waveform from the clock generator can be selected to be an output clock in accordance with an error signal determined by a difference between a level of data in a buffer and a predetermined threshold. The output clock can also be a timing reference waveform for data removed from the buffer. In another embodiment, the error signal can be determined periodically. In yet another embodiment, the output clock domain can be different from the input clock domain of the buffer.
摘要翻译：时钟合成装置的一个实施例可以包括可以提供两个或更多个时钟波形的时钟发生器。来自时钟发生器的一个时钟波形可以根据由缓冲器中的数据量与预定阈值之间的差确定的误差信号来选择为输出时钟。输出时钟也可以是从缓冲器中删除的数据的定时参考波形。在另一个实施例中，可以周期性地确定误差信号。在另一个实施例中，输出时钟域可以不同于缓冲器的输入时钟域。

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