专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11592889B2 Die-to-die dynamic clock and power gating 有权
公开(公告)号：US11592889B2
公开(公告)日：2023-02-28
申请号：US17318670
申请日：2021-05-12
申请人： Apple Inc.
发明人： Dany Davidov , Misbah Ramadan , Itamar Rozen , Tzach Zemer
IPC分类号： G06F1/3203 , G06F1/18 , G06F13/36 , G06F13/40
摘要： A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

2. 发明公开

US20230350828A1 Multiple Independent On-chip Interconnect 审中-公开
公开(公告)号：US20230350828A1
公开(公告)日：2023-11-02
申请号：US18309192
申请日：2023-04-28
申请人： Apple Inc.
发明人： Sergio Kolor , Sergio V. Tota , Tzach Zemer , Sagi Lahav , Jonathan M. Redshaw , Per H. Hammarlund , Eran Tamari , James Vash , Gaurav Garg , Lior Zimet , Harshavardhan Kaushikkar , Steven Fishwick , Steven R. Hutsell , Shawn M. Fukami
IPC分类号： G06F15/173 , G06F13/40
CPC分类号： G06F13/4027 , G06F13/4022 , G06F15/17375 , G06F15/17381
摘要： In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

3. 发明申请

US20220334997A1 Multiple Independent On-chip Interconnect 有权
公开(公告)号：US20220334997A1
公开(公告)日：2022-10-20
申请号：US17337805
申请日：2021-06-03
申请人： Apple Inc.
发明人： Sergio Kolor , Sergio V. Tota , Tzach Zemer , Sagi Lahav , Jonathan M. Redshaw , Per H. Hammarlund , Eran Tamari , James Vash , Gaurav Garg
IPC分类号： G06F13/40 , G06F15/173
摘要： In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

4. 发明授权

US10038425B1 Sum of differences filter 有权
公开(公告)号：US10038425B1
公开(公告)日：2018-07-31
申请号：US14980577
申请日：2015-12-28
申请人： Apple Inc.
发明人： Tzach Zemer , Louie Matar , Emmanuel Elder
IPC分类号： H03H17/02 , G10L21/0264
CPC分类号： H03H17/0223 , H03H17/06 , H03H17/0664
摘要： Systems, apparatuses, and methods for implementing a low power filter. A low power filter may generate a reference sum from a reference vector in order to reduce the number of additions which are needed to filter an input sample vector. The reference sum may be used as the starting point for filtering the input sample vector. Then, each input sample of the input sample vector may be compared to a corresponding reference vector sample. If an input sample is different from the corresponding reference vector sample, a correction value based on the corresponding filter coefficient value may be added or subtracted from the reference sum. After all input samples have been compared to corresponding reference vector values and all correction values applied to the reference sum, the modified reference sum may be the output of the filter.

5. 发明授权

US10048893B2 Clock/power-domain crossing circuit with asynchronous FIFO and independent transmitter and receiver sides 有权
公开(公告)号：US10048893B2
公开(公告)日：2018-08-14
申请号：US14706076
申请日：2015-05-07
申请人： Apple Inc.
发明人： Mark Goikhman , Tzach Zemer
IPC分类号： H05K7/10 , G06F13/00 , G06F13/28 , G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00 , G06F3/00 , G06F5/00 , G06F13/36 , G06F3/06 , G06F13/40
摘要： An electronic circuit includes transmit-side circuitry and receive-side circuitry. The transmit-side circuitry belongs to a first domain of the circuit and is configured to transmit a data signal from the first domain to a second domain of the circuit. The receive-side circuitry belongs to the second domain and is configured to receive the transmitted data signal. The receive-side circuitry is configured to transfer to the transmit-side circuitry a read pointer value indicative of a readout position in a buffer memory that buffers the data signal, and to retain the read pointer value in a non-volatile element that is accessible to the transmit-side circuitry.

6. 发明申请

US20170054433A1 LOW POWER DECIMATOR 有权
标题翻译：低功率减速机
公开(公告)号：US20170054433A1
公开(公告)日：2017-02-23
申请号：US14831708
申请日：2015-08-20
申请人： APPLE INC.
发明人： Tzach Zemer , Joseph J. Cheng
IPC分类号： H03H17/06 , H04R3/04
CPC分类号： H03H17/0664 , H03H17/0226 , H04R3/00 , H04R3/04 , H04R2410/00
摘要： Systems, apparatuses, and methods for implementing a low power decimator. A decimator may receive a plurality of input samples from a digital microphone. The decimator may include one or more coefficient tables for storing values combining two or more filter coefficients for filtering the received samples. The decimator may utilize a concatenation of multiple samples to perform a lookup of a corresponding coefficient table. The coefficient tables may store only the necessary non-redundant values for all coefficient combinations which can be applied to the multiple samples. The result of the lookup of the coefficient table may have its sign inverted or be zeroed based on the values of the multiple samples.
摘要翻译：用于实现低功率抽取器的系统，设备和方法。抽取器可以从数字麦克风接收多个输入样本。抽取器可以包括一个或多个系数表，用于存储组合用于过滤所接收的样本的两个或更多个滤波器系数的值。抽取器可以利用多个样本的级联来执行对应系数表的查找。系数表可以仅存储可应用于多个样本的所有系数组合所需的非冗余值。系数表查找的结果可以根据多个样本的值反转或归零。

7. 发明申请

US20160328182A1 CLOCK/POWER-DOMAIN CROSSING CIRCUIT WITH ASYNCHRONOUS FIFO AND INDEPENDENT TRANSMITTER AND RECEIVER SIDES 审中-公开
标题翻译：具有异步FIFO和独立发送器和接收端的时钟/电源域交叉电路
公开(公告)号：US20160328182A1
公开(公告)日：2016-11-10
申请号：US14706076
申请日：2015-05-07
申请人： Apple Inc.
发明人： Mark Goikhman , Tzach Zemer
IPC分类号： G06F3/06 , G06F13/40
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0688 , G06F13/4027
摘要： An electronic circuit includes transmit-side circuitry and receive-side circuitry. The transmit-side circuitry belongs to a first domain of the circuit and is configured to transmit a data signal from the first domain to a second domain of the circuit. The receive-side circuitry belongs to the second domain and is configured to receive the transmitted data signal. The receive-side circuitry is configured to transfer to the transmit-side circuitry a read pointer value indicative of a readout position in a buffer memory that buffers the data signal, and to retain the read pointer value in a non-volatile element that is accessible to the transmit-side circuitry.
摘要翻译：电子电路包括发射侧电路和接收侧电路。发射侧电路属于电路的第一域，并且被配置为将数据信号从第一域发送到电路的第二域。接收侧电路属于第二域，并被配置为接收发送的数据信号。接收侧电路被配置为向发送侧电路传送指示缓冲存储器中的缓冲存储器中的读出位置的读指针值，并且将读指针值保持在可访问的非易失性元件中发送侧电路。

8. 发明公开

US20240085968A1 Dynamic Interface Circuit to Reduce Power Consumption 审中-公开
公开(公告)号：US20240085968A1
公开(公告)日：2024-03-14
申请号：US18175900
申请日：2023-02-28
申请人： Apple Inc.
发明人： Tzach Zemer , Lior Zimet , Sagi Lahav
IPC分类号： G06F1/3206 , G06F1/08 , G06F1/3234 , H04W52/02
CPC分类号： G06F1/3206 , G06F1/08 , G06F1/3234 , H04W52/02
摘要： A system for a given device may include a plurality of systems on a chip (SOCs). Each SOC may include an interface circuit and a bridge circuit for communicating with other SOCs. The interface circuit of an SOC may include a plurality of communication devices to transfer data packets from/to the SOC to the other SOCs. The bridge circuit may provide various control functions for the interface circuit. An indication may be generated when the system enters an idle mode. In response, the bridge circuit may generate signal(s) to cause some of the communication devices of the interface circuit into a low power state. The interface circuit may obtain the signal(s) and accordingly transition some of the communication devices to the low power state.

9. 发明公开

US20230239252A1 Segment to Segment Network Interface 审中-公开
公开(公告)号：US20230239252A1
公开(公告)日：2023-07-27
申请号：US17868495
申请日：2022-07-19
申请人： Apple Inc.
发明人： Sergio Kolor , Lior Zimet , Opher D. KAHN , Eran Tamari , Tzach Zemer , Per H. Hammarlund
IPC分类号： H04L49/25 , H04L47/10
CPC分类号： H04L49/25 , H04L47/39
摘要： In an embodiment, a system includes a plurality of integrated circuits have subsets of a plurality of agents. The plurality of integrated circuits may have network segments implemented wholly (e.g., entirely) within the respective integrated circuits and may have segment to segment (S2S) network interface circuits to couple to other network segments of a plurality of network segment forming a network among the plurality of agents.

10. 发明公开

US20230214350A1 Die-to-die Dynamic Clock and Power Gating 审中-公开
公开(公告)号：US20230214350A1
公开(公告)日：2023-07-06
申请号：US18174985
申请日：2023-02-27
申请人： Apple Inc.
发明人： Dany Davidov , Misbah Ramadan , Itamar Rozen , Tzach Zemer
IPC分类号： G06F13/42 , G06F9/30 , G06F13/40
CPC分类号： G06F13/4291 , G06F9/30083 , G06F13/4022
摘要： A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式