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1. 发明授权

US10930201B1 Micro light emitting diode testing 有权
公开(公告)号：US10930201B1
公开(公告)日：2021-02-23
申请号：US15910906
申请日：2018-03-02
申请人： Apple Inc.
发明人： Mahdi Farrokh Baroughi , Bo Yang , Xiang Lu , Hopil Bae
IPC分类号： G09G3/32 , G09G3/00
摘要： Methods and systems for testing a display having an array of microdrivers arranged in multiple of rows and columns including setting a testing mode of a microdriver of the array of microdrivers using multiple pins of the microdriver that are used in scanning or operation modes of the microdriver. The microdriver is configured to light one or more connected micro light emitting diode pixels coupled to the microdriver during the testing mode. Testing also includes operating the microdriver in the testing mode and determining functionality of the one or more connected micro light emitting diode pixels or the microdriver based on the testing mode.

2. 发明授权

US10891882B1 Techniques for testing electrically configurable digital displays, and associated display architecture 有权
公开(公告)号：US10891882B1
公开(公告)日：2021-01-12
申请号：US15910886
申请日：2018-03-02
申请人： Apple Inc.
发明人： Mahdi Farrokh Baroughi , Mohammad B. Vahid Far , Xiang Lu , Bo Yang , Derek K. Shaeffer , Henry C. Jen , Hopil Bae
IPC分类号： G09G3/00 , G09G3/36
摘要： The present techniques are capable of identifying and pinpointing defective microdrivers and/or row/column drivers either before or after any μLEDs have been placed on the display. Using the architectures described herein, test data may be delivered in a parallel fashion to the drivers from support circuitry, such as a timing controller and/or a main board, and outputs based on the test data may be similarly delivered back to the support circuitry do determine which drivers are defective. This yields access to the output of every microdriver and row drier, thus enabling the identification of specific defective elements.

3. 发明授权

US10859628B2 Power droop measurements using analog-to-digital converter during testing 有权
公开(公告)号：US10859628B2
公开(公告)日：2020-12-08
申请号：US16375344
申请日：2019-04-04
申请人： Apple Inc.
发明人： Bibo Li , Bo Yang , Vijay M. Bettada , Matthias Knoth , Toshinari Takayanagi
IPC分类号： G01R31/317 , G01R19/00 , H03M1/12 , G01R31/3177
摘要： An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

4. 发明授权

US09658634B2 Under voltage detection and performance throttling 有权
公开(公告)号：US09658634B2
公开(公告)日：2017-05-23
申请号：US14673326
申请日：2015-03-30
申请人： Apple Inc.
发明人： Brijesh Tripathi , Eric G. Smith , Erik P. Machnicki , Jung Wook Cho , Khaled M. Alashmouny , Kiran B. Kattel , Vijay M. Bettada , Bo Yang , Wenlong Wei
IPC分类号： G06F1/00 , G05F3/02 , G06F1/32
CPC分类号： G05F3/02 , G06F1/324 , G06F1/3296
摘要： An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

5. 发明申请

US20200026345A1 COMPUTER SYSTEM POWER MONITORING 审中-公开
公开(公告)号：US20200026345A1
公开(公告)日：2020-01-23
申请号：US16039842
申请日：2018-07-19
申请人： Apple Inc.
发明人： Jay B. Fletcher , Karthik Manickam , Bo Yang , Vincent R. von Kaenel , Shawn Searles , Hubert Attah , Nir Dahan , Olivier Girard
IPC分类号： G06F1/32 , G01R31/28
摘要： A voltage regulator circuit included in a computer system may generate a voltage level on a power supply signal using a source power supply signal and based initial values of one or more operation parameters derived from wafer-level test data. One or more operation characteristics of the voltage regulator circuit may be sampled, by a measurement circuit, at multiple time points to generated measurement data. A control circuit may adapt operation of the voltage regulator circuit based on the measurement data.

6. 发明授权

US09892802B1 Hardware assisted scheme for testing memories using scan 有权
公开(公告)号：US09892802B1
公开(公告)日：2018-02-13
申请号：US14714381
申请日：2015-05-18
申请人： Apple Inc.
发明人： Bo Yang , Andrew J. Copperhall , Bibo Li , Vijay M. Bettada
IPC分类号： G11C29/10 , G01R31/3177 , G11C29/50
CPC分类号： G11C29/10 , G01R31/3177
摘要： A hardware assisted scheme for testing IC memories using scan circuitry is disclosed. An IC includes a memory implemented thereon and a chain of serially-coupled scan elements to enable the inputting of test vectors. The scan elements include first and second subsets forming write and read address registers, respectively, a first control flop, and a second control flop. During a launch cycle of a test operation, a first address loaded into the write address register is provided to a write address decoder to effect a write operation. Also responsive to the launch cycle, the first control flop is configured to cause the first address to be provided to the read address register, while the second control flop causes data to be written into the memory. During a capture cycle, the first address is provided to a read address decoder and the second control flop causes a read of data therefrom.

7. 发明申请

US20160291625A1 Under Voltage Detection and Performance Throttling 有权
标题翻译：欠压检测和性能调节
公开(公告)号：US20160291625A1
公开(公告)日：2016-10-06
申请号：US14673326
申请日：2015-03-30
申请人： Apple Inc.
发明人： Brijesh Tripathi , Eric G. Smith , Erik P. Machnicki , Jung Wook Cho , Khaled M. Alashmouny , Kiran B. Kattel , Vijay M. Bettada , Bo Yang , Wenlong Wei
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , G06F1/324 , G06F1/3296
摘要： An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.
摘要翻译：公开了一种欠压检测电路及其运算方法。在一个实施例中，IC包括欠压保护电路，其具有第一和第二比较器，其被配置为分别将电源电压与第一和第二电压阈值进行比较，其中第二电压阈值大于第一电压阈值。逻辑电路被耦合以从第一和第二比较器接收信号。在通过相应的功能电路在高性能状态下操作期间，逻辑电路被配置为响应于电源电压已经低于第一阈值的指示而导致节流信号的断言。提供给功能电路的时钟信号可以响应于指示而被节流。如果电源电压随后上升到高于第二阈值的水平，则节流信号可以被取消断言。

8. 发明申请

US20160091564A1 COMPRESSED SCAN TESTING TECHNIQUES 有权
标题翻译：压缩扫描测试技术
公开(公告)号：US20160091564A1
公开(公告)日：2016-03-31
申请号：US14502284
申请日：2014-09-30
申请人： Apple Inc.
发明人： Bibo Li , Andrew J. Copperhall , Bo Yang
IPC分类号： G01R31/3177
CPC分类号： G01R31/318566 , G01R31/318544
摘要： Techniques are disclosed relating to test equipment. In one embodiment, a method includes receiving failure information from a first test of a device under test (DUT). In this embodiment, the DUT includes a plurality of scan chains that each include a plurality of scan cells. In this embodiment, the first test is based on a first compressed test pattern. In this embodiment, the failure information does not permit a definitive determination as to which scan cell is a failing scan cell. In this embodiment, the method includes generating a plurality of compressed test patterns based on the first compressed test pattern. In this embodiment, the plurality of compressed test patterns specify one-to-one-modes. In this embodiment, the method includes performing one or more second tests of the DUT using the plurality of compressed test patterns to definitively determine one or more failing scan cells.
摘要翻译：公开了与测试设备有关的技术。在一个实施例中，一种方法包括从被测设备（DUT）的第一测试接收故障信息。在该实施例中，DUT包括多个扫描链，每条扫描链包括多个扫描单元。在该实施例中，第一测试基于第一压缩测试图案。在本实施例中，故障信息不能确定哪个扫描单元是故障扫描单元。在该实施例中，该方法包括基于第一压缩测试图案生成多个压缩测试图案。在该实施例中，多个压缩测试图案指定一对一模式。在该实施例中，该方法包括使用多个压缩测试模式来执行DUT的一个或多个第二测试，以确定确定一个或多个故障扫描单元。

9. 发明申请

US20200319248A1 POWER DROOP MEASUREMENTS USING ANALOG-TO-DIGITAL CONVERTER DURING TESTING 审中-公开
公开(公告)号：US20200319248A1
公开(公告)日：2020-10-08
申请号：US16375344
申请日：2019-04-04
申请人： Apple Inc.
发明人： Bibo Li , Bo Yang , Vijay M. Bettada , Matthias Knoth , Toshinari Takayanagi
IPC分类号： G01R31/317 , G01R19/00 , G01R31/3177 , H03M1/12
摘要： An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

10. 发明授权

US10891884B1 Test-response comparison circuit and scan data transfer scheme in a DFT architecture for micro LED based display panels 有权
公开(公告)号：US10891884B1
公开(公告)日：2021-01-12
申请号：US16281996
申请日：2019-02-21
申请人： Apple Inc.
发明人： Bo Yang , Xiang Lu , Andrew J. Copperhall , Henry C. Jen , Karthik Manickam , Sagar Nataraj , Shriram Vijayakumar , Derek K. Shaeffer
IPC分类号： G09G3/00 , G09G3/32 , G01R31/3185 , G01R31/317 , G01R31/58
摘要： Design-for-test (DFT) architectures, and methods of testing an array of chips, which may be identical, are described. In an embodiment, a comparison circuit includes a plurality of comparators to compare scan-data out (SDO) data streams with an expected data stream and transmit a compared data stream that is indicated of whether or not an error exists in any of the SDO data streams.

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