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1. 发明申请

US20050035468A1 Semiconductor electronic device and method of manufacturing thereof 有权
标题翻译：半导体电子器件及其制造方法
公开(公告)号：US20050035468A1
公开(公告)日：2005-02-17
申请号：US10864901
申请日：2004-06-09
申请人： Antonio Andreini , Lorenzo Cerati , Paola Galbiati , Alessandra Merlini
发明人： Antonio Andreini , Lorenzo Cerati , Paola Galbiati , Alessandra Merlini
IPC分类号： H01L23/485 , H01L23/48
CPC分类号： H01L24/06 , H01L24/03 , H01L24/05 , H01L2224/04042 , H01L2224/05083 , H01L2224/05552 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/12036 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor electronic device is described comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support for example through interposition of contact wires, said plurality of contact pads comprising signal pads and power pads, the device being characterized in that said signal pads are implemented on the die of semiconductor material with a mutual pitch lower than the pitch between said power pads.
摘要翻译：描述了一种半导体电子器件，其包括具有多个接触焊盘的半导体材料的管芯，例如通过插入接触导线电连接到支撑件，所述多个接触焊盘包括信号焊盘和电源焊盘，该器件的特征在于所述信号焊盘实现在半导体材料的裸片上，其相互间距低于所述电源焊盘之间的间距。

2. 发明授权

US07126230B2 Semiconductor electronic device and method of manufacturing thereof 有权
标题翻译：半导体电子器件及其制造方法
公开(公告)号：US07126230B2
公开(公告)日：2006-10-24
申请号：US10864901
申请日：2004-06-09
申请人： Antonio Andreini , Lorenzo Cerati , Paola Galbiati , Alessandra Merlini
发明人： Antonio Andreini , Lorenzo Cerati , Paola Galbiati , Alessandra Merlini
IPC分类号： H01L29/40
CPC分类号： H01L24/06 , H01L24/03 , H01L24/05 , H01L2224/04042 , H01L2224/05083 , H01L2224/05552 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/12036 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor electronic device is described comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support for example through interposition of contact wires, said plurality of contact pads comprising signal pads and power pads, the device being characterized in that said signal pads are implemented on the die of semiconductor material with a mutual pitch lower than the pitch between said power pads.
摘要翻译：描述了一种半导体电子器件，其包括具有多个接触焊盘的半导体材料的管芯，例如通过插入接触导线电连接到支撑件，所述多个接触焊盘包括信号焊盘和电源焊盘，该器件的特征在于所述信号焊盘实现在半导体材料的裸片上，其相互间距低于所述电源焊盘之间的间距。

3. 发明授权

US06538281B2 Low on-resistance LDMOS 有权
标题翻译：低导通电阻LDMOS
公开(公告)号：US06538281B2
公开(公告)日：2003-03-25
申请号：US09862750
申请日：2001-05-22
申请人： Giuseppe Croce , Alessandro Moscatelli , Alessandra Merlini , Paola Galbiati
发明人： Giuseppe Croce , Alessandro Moscatelli , Alessandra Merlini , Paola Galbiati
IPC分类号： H01L31119
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/41758 , H01L29/41775 , H01L29/4238 , H01L29/456
摘要： An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.
摘要翻译： LDMOS结构形成在半导体衬底的第一导电类型的区域中，并且包括栅极，漏极区域和源极区域。源极区域由第一区域内的第二导电类型的体扩散形成，并且第一类型的导电性的源极扩散在体扩散内。第二类导电性的电连接扩散是源极区域的有限区域，并且延伸穿过源极扩散并且向下延伸到身体扩散。源扩散和电连接扩散至少有一个源触点。 LDMOS结构还包括在源极区域的整个区域上的硅化物层，使源扩散和电连接扩散短路。源极接触形成在硅化物层上。

4. 发明授权

US07005336B2 Process for forming CMOS transistors and MOS transistors of the drain extension type, with a low gate region resistance, in the same semiconductor substrate 有权
标题翻译：在相同的半导体衬底中形成具有低栅极区电阻的漏极延伸型的CMOS晶体管和MOS晶体管的工艺
公开(公告)号：US07005336B2
公开(公告)日：2006-02-28
申请号：US10746881
申请日：2003-12-23
申请人： Alessandro Moscatelli , Claudia Raffaglio , Alessandra Merlini , M. Paola Galbiati
发明人： Alessandro Moscatelli , Claudia Raffaglio , Alessandra Merlini , M. Paola Galbiati
IPC分类号： H01L21/8238 , H01L21/461 , H01L21/302
CPC分类号： H01L29/6659 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/66659 , H01L29/7835
摘要： A process is disclosed for forming, on a common semiconductor substrate, CMOS transistors and vertical or lateral MOS transistors on at least first and second portions, respectively, of the substrate. A first dielectric layer is formed on the substrate. A first semiconductor material layer is then formed on the first dielectric layer, in the first portion. A stack structure comprising a second dielectric layer, second semiconductor layer, and low-resistance layer is then formed over the substrate. First ports are defined in the second semiconductor layer and the low-resistance layer to provide gate regions of the vertical or lateral MOS transistors. The second semiconductor layer and the low-resistance layer are then removed from the first portion of the substrate by using the second dielectric layer as a screen. Second ports in the second dielectric layer and the second semiconductor layer are then defined to provide gate regions for the CMOS transistors. The gate region of the vertical or lateral transistors is then covered with a protective layer. A low-resistance layer is then formed on the gate regions of the CMOS transistors.
摘要翻译：公开了一种在公共半导体衬底上分别在衬底的至少第一和第二部分上形成CMOS晶体管和垂直或横向MOS晶体管的工艺。在基板上形成第一电介质层。在第一部分中，在第一介电层上形成第一半导体材料层。然后在衬底上形成包括第二电介质层，第二半导体层和低电阻层的堆叠结构。第一端口被限定在第二半导体层和低电阻层中，以提供垂直或横向MOS晶体管的栅极区域。然后通过使用第二介电层作为屏幕，从基板的第一部分去除第二半导体层和低电阻层。然后限定第二介电层和第二半导体层中的第二端口以为CMOS晶体管提供栅极区域。然后用保护层覆盖垂直或横向晶体管的栅极区域。然后在CMOS晶体管的栅极区域上形成低电阻层。

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