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1. 发明授权

US5479364A Method and arrangement for transformation of signals from a frequency to a time domain 失效
标题翻译：信号从频率变换到时域的方法和装置
公开(公告)号：US5479364A
公开(公告)日：1995-12-26
申请号：US82087
申请日：1993-06-24
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译： IDCT或逆离散余弦变换方法将2-D IDCT分解成两个1-D IDCT操作，然后分别对偶数和奇数像素输入字进行操作。在通常的处理步骤中，所选择的输入值直接传递到输出加法器和减法器，而其他输入值乘以恒定的缩放余弦值。在预共同处理步骤中，最低阶奇数输入字被预先乘以2ROOT 2，并且奇数输入字在公共处理步骤中处理之前成对加法。在公知处理步骤中，将与处理的奇数输入字对应的中间值乘以预定系数，以形成奇数合成值。在偶数和奇数结果值的计算之后，高次和低阶输出分别由奇偶结果值/偶数结果值的简单减法/加法形成。输入值优选地向上按比例2ROOT 2.通过将这些位强制为“1”或“0”可选地调整某些中间结果数据字的选定位。 IDCT系统包括在各步骤中执行必要操作的预共同处理电路（PREC），公共处理电路（CBLK）和后公共处理电路（POSTC）。该系统还包括用于产生信号以控制系统锁存器的加载的控制器（CNTL），并且优选地将偶数和奇数输入字的应用时间复用到预共同电路中的锁存器。

2. 发明授权

US5590067A Method and arrangement for transformation of signals from a frequency to a time domain 失效
标题翻译：信号从频率变换到时域的方法和装置
公开(公告)号：US5590067A
公开(公告)日：1996-12-31
申请号：US404067
申请日：1995-03-14
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot. 2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot. 2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译： IDCT方法将2-D IDCT分解成两个1-D IDCT操作，然后分别对偶数和奇数像素输入字进行操作。在通常的处理步骤中，所选择的输入值直接传递到输出加法器和减法器，而其他输入值乘以恒定的缩放余弦值。在预共同处理步骤中，最低阶奇数输入字被预先乘以2ROOT + E，rad + EE 2，并且奇数输入字在公共处理步骤中处理之前成对相加。在公知处理步骤中，将与处理的奇数输入字对应的中间值乘以预定系数，以形成奇数合成值。在偶数和奇数结果值的计算之后，高次和低阶输出分别由奇偶结果值/偶数结果值的简单减法/加法形成。输入值优选地按照2ROOT + E，rad + EE2的因子向上扩展。通过将这些位强制为“1”或“0”，可选地调整一些中间结果数据字的选定位。 IDCT系统包括在各步骤中执行必要操作的预共同处理电路（PREC），公共处理电路（CBLK）和后公共处理电路（POSTC）。该系统还包括用于产生信号以控制系统锁存器的加载的控制器（CNTL），并且优选地将偶数和奇数输入字的应用时间复用到预共同电路中的锁存器。

3. 发明授权

US5596517A Method and arrangement for transformation of signals from a frequency to a time domain 失效
公开(公告)号：US5596517A
公开(公告)日：1997-01-21
申请号：US400722
申请日：1995-03-07
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.

4. 发明授权

US5594678A Method and arrangement for transformation of signals from a frequency to a time domain 失效
标题翻译：信号从频率变换到时域的方法和装置
公开(公告)号：US5594678A
公开(公告)日：1997-01-14
申请号：US400723
申请日：1995-03-07
申请人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
发明人： Anthony M. Jones , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N1/41 , G06F17/14 , G06T1/20 , H04N7/30 , G06F7/38
CPC分类号： G06F17/147
摘要： An IDCT, or Inverse Discrete Cosine Transform, method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by .sqroot.2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of .sqroot.2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0". The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译： IDCT或逆离散余弦变换方法将2-D IDCT分解成两个1-D IDCT操作，然后分别对偶数和奇数像素输入字进行操作。在通常的处理步骤中，所选择的输入值直接传递到输出加法器和减法器，而其他输入值乘以恒定的缩放余弦值。在预共同处理步骤中，最低阶奇数输入字被预先乘以2ROOT + E，rad 2 + EE，并且奇数输入字在公共处理步骤中处理之前成对地相加。在公知处理步骤中，将与处理的奇数输入字对应的中间值乘以预定系数，以形成奇数合成值。在偶数和奇数结果值的计算之后，高次和低阶输出分别由奇偶结果值/偶数结果值的简单减法/加法形成。输入值优选地向上扩展2ROOT + E，rad 2 + EE的因子。通过强制这些位为“1”或“0”可选地调整一些中间结果数据字的选定位。 IDCT系统包括在各步骤中执行必要操作的预共同处理电路（PREC），公共处理电路（CBLK）和后公共处理电路（POSTC）。该系统还包括用于产生信号以控制系统锁存器的加载的控制器（CNTL），并且优选地将偶数和奇数输入字的应用时间复用到预共同电路中的锁存器。

5. 发明授权

US5963154A Technique for decoding variable and fixed length codes 失效
标题翻译：解码变量和固定长度代码的技术
公开(公告)号：US5963154A
公开(公告)日：1999-10-05
申请号：US484170
申请日：1995-06-07
申请人： Adrian P. Wise , Kevin D. Dewar , Martin W. Sotheran
发明人： Adrian P. Wise , Kevin D. Dewar , Martin W. Sotheran
IPC分类号： H04N5/92 , G06F3/14 , G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/08 , G06F13/00 , G06F13/16 , G06F13/28 , G06F13/37 , G06T9/00 , G11B7/00 , G11B27/10 , H03M7/30 , H03M7/40 , H03M7/42 , H04L7/00 , H04L7/08 , H04L12/433 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/52
CPC分类号： H04N21/4307 , G06F12/0207 , G06F13/16 , G06F13/28 , H04N19/42 , H04N19/423 , H04N19/61 , H04N21/4305 , H04N21/44004 , G06F12/04 , H04N19/13 , H04N19/91
摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
摘要翻译：一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等。

6. 发明授权

US06910125B2 Multistandard video decoder and decompression system for processing encoded bit streams including a decoder with token generator and methods relating thereto 失效
标题翻译：用于处理编码比特流的多标准视频解码器和解压缩系统，包括具有令牌生成器的解码器和与其相关的方法
公开(公告)号：US06910125B2
公开(公告)日：2005-06-21
申请号：US09777283
申请日：2001-02-06
申请人： Adrian P. Wise , Martin W. Sotheran , William P. Robbins , Anthony M. Jones , Anthony Peter John Claydon , Kevin Boyd , Helen R. Finch
发明人： Adrian P. Wise , Martin W. Sotheran , William P. Robbins , Anthony M. Jones , Anthony Peter John Claydon , Kevin Boyd , Helen R. Finch
IPC分类号： G06F7/00 , G06F9/38 , G06F9/44 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/16 , G06F13/28 , G06T9/00 , H04N7/26 , H04N7/50 , G06F15/00 , G06F7/08 , G06F7/24 , G06F7/36
CPC分类号： G06F9/3867 , G06F9/4494 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/16 , G06F13/1673 , G06F13/1689 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto.
摘要翻译：流水线视频解码器和解压缩系统处理多个单独编码的比特流，其被布置为数字比特的单个串行比特流，并且具有单独编码的控制码对和串行比特流中携带的对应数据。流水线系统采用多个互连的级来解码和解压缩单个比特流，包括起始码检测器。当处于搜索模式时，起始代码检测器搜索与多个压缩标准之一相对应的特定开始代码。响应于单个串行比特流的起始码检测器产生控制令牌和数据令牌。相应的令牌包括多个数据字。每个数据字具有指示其中存在附加字的扩展位。因此数据字数量无限。定位在某些阶段的令牌解码电路将某些令牌识别为与该级相关的控制令牌，并将未被识别的控制令牌传递到后续级。定位在某些阶段的可重构解码和解析器处理装置响应于识别的控制令牌，并且重新配置特定级以处理所识别的数据令牌。与解码器和解压缩系统相关的方法包括与其相关的处理步骤。

7. 发明授权

US06417859B1 Method and apparatus for displaying video data 有权
标题翻译：用于显示视频数据的方法和装置
公开(公告)号：US06417859B1
公开(公告)日：2002-07-09
申请号：US09323627
申请日：1999-06-01
申请人： Martin W. Sotheran , Helen Rosemary Finch
发明人： Martin W. Sotheran , Helen Rosemary Finch
IPC分类号： G09G500
CPC分类号： G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/16 , G06F13/28 , H04N19/423 , H04N19/61
摘要： This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number.
摘要翻译：本发明提供一种控制被组织为帧或场的编码视频数据的缓冲的方法。该方法包括确定每个输入的解码帧的图像号码，在任何时间确定预期的呈现号码，并且当其图像号码在呈现号码之后或之后将任何缓冲器标记为就绪。

8. 发明授权

US06892296B2 Multistandard video decoder and decompression system for processing encoded bit streams including a standard-independent stage and methods relating thereto 失效
标题翻译：用于处理编码比特流的多标准视频解码器和解压缩系统，包括与标准无关的阶段和与之有关的方法
公开(公告)号：US06892296B2
公开(公告)日：2005-05-10
申请号：US09773473
申请日：2001-02-01
申请人： Adrian P. Wise , Kevin Boyd , Anothy Peter Claydon , William P. Robbins , Helen R. Finch , Martin W. Sotheran , Anthony Mark Jones
发明人： Adrian P. Wise , Kevin Boyd , Anothy Peter Claydon , William P. Robbins , Helen R. Finch , Martin W. Sotheran , Anthony Mark Jones
IPC分类号： G06F7/00 , G06F9/38 , G06F9/44 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/16 , G06F13/28 , G06T9/00 , H04N7/26 , H04N7/50 , G06F15/00 , G06F7/08 , G06F7/24 , G06F7/36
CPC分类号： G06F9/3867 , G06F9/4494 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/16 , G06F13/1673 , G06F13/1689 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto.
摘要翻译：流水线视频解码器和解压缩系统处理多个单独编码的比特流，其被布置为数字比特的单个串行比特流，并且具有单独编码的控制码对和串行比特流中携带的对应数据。流水线系统采用多个互连的级来解码和解压缩单个比特流，包括起始码检测器。当处于搜索模式时，起始代码检测器搜索与多个压缩标准之一相对应的特定开始代码。响应于单个串行比特流的起始码检测器产生控制令牌和数据令牌。相应的令牌包括多个数据字。每个数据字具有指示其中存在附加字的扩展位。因此数据字数量无限。定位在某些阶段的令牌解码电路将某些令牌识别为与该级相关的控制令牌，并将未被识别的控制令牌传递到后续级。定位在某些阶段的可重构解码和解析器处理装置响应于识别的控制令牌，并且重新配置特定级以处理所识别的数据令牌。与解码器和解压缩系统相关的方法包括与其相关的处理步骤。

9. 发明授权

US06263422B1 Pipeline processing machine with interactive stages operable in response to tokens and system and methods relating thereto 失效
标题翻译：具有可响应于令牌和与之相关的系统和方法可操作的交互式阶段的管道处理机
公开(公告)号：US06263422B1
公开(公告)日：2001-07-17
申请号：US08484730
申请日：1995-06-07
申请人： Adrian P. Wise , Martin W. Sotheran , William P. Robbins
发明人： Adrian P. Wise , Martin W. Sotheran , William P. Robbins
IPC分类号： G06F930
CPC分类号： G06F9/3867 , G06F9/4494 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/16 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/61 , H04N19/91
摘要： A plurality of processing stages interposed between an input and an output of a system including a pipeline machine interconnect for conveyance of tokens along the pipeline. Control and or data tokens in the form of universal adaptation units interface with all of the stages in the pipeline and alternatively interact with selected stages in the pipeline so that the processing stages in the pipeline are afforded enhanced flexibility in configuration and processing. In one embodiment of the system, the stages accept a data stream having portions encoded according to respectively different video formats. At least one of the stages includes circuitry for generating signals to indicate an end-of-picture data decoding. The stage includes state machine logic that is responsive to the generated signals for effecting an end of picture data decoding by clearing the pipeline. A method of clearing the pipeline includes receiving a data stream, indicating an end of picture data decoding, and clearing the pipeline when an end of picture data decoding has been indicated.
摘要翻译：多个处理台，其插入在包括管道机器互连的系统的输入和输出之间，用于沿管道输送令牌。以通用适配单元形式的控制和/或数据令牌与流水线中的所有阶段接口，并且交替地与流水线中的选定阶段进行交互，从而提供流水线处理阶段在配置和处理方面的增强灵活性。在系统的一个实施例中，阶段接受具有根据分别不同的视频格式编码的部分的数据流。至少一个级包括用于产生信号以指示画面结束数据解码的电路。舞台包括响应于所产生的信号的状态机逻辑，以通过清除流水线来实现图像数据解码的结束。清除流水线的方法包括：当已经指示图像数据解码结束时，接收指示图像数据解码结束的数据流，以及清除流水线。

10. 发明授权

US5603012A Start code detector 失效
标题翻译：起始代码检测器
公开(公告)号：US5603012A
公开(公告)日：1997-02-11
申请号：US400201
申请日：1995-03-07
申请人： Martin W. Sotheran
发明人： Martin W. Sotheran
IPC分类号： G06F7/00 , G06F9/38 , G06F9/44 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/16 , G06F13/28 , G06T9/00 , H04N7/26 , H04N7/50 , G06F13/37
CPC分类号： G06F9/3867 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/16 , G06F13/1673 , G06F13/1689 , G06F13/28 , G06F9/4436 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/13 , H04N19/91
摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.
摘要翻译：多标准视频解压缩装置具有通过布置为流水线处理机的两线接口互连的多个级。控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。公开了各种独特的支持子系统电路和处理技术来实现该系统。

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