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1. 发明授权

US07102555B2 Boundary-scan circuit used for analog and digital testing of an integrated circuit 有权
标题翻译：用于集成电路模拟和数字测试的边界扫描电路
公开(公告)号：US07102555B2
公开(公告)日：2006-09-05
申请号：US10837171
申请日：2004-04-30
申请人： Anthony J. Collins , David P. Schultz , Neil G. Jacobson , Edward S. McGettigan , Bradley K. Fross
发明人： Anthony J. Collins , David P. Schultz , Neil G. Jacobson , Edward S. McGettigan , Bradley K. Fross
IPC分类号： H03M1/10 , G01R31/28
CPC分类号： G01R31/3167 , G01R31/318555
摘要： Method and apparatus are described for providing analog capability with boundary-scanning for an integrated circuit. The integrated circuit includes a boundary-scan controller (1517) coupled to an analog-to-digital converter (200). An analog channel is selected for input to the analog-to-digital converter (200). Analog information is converted to digital information by the analog-to-digital converter (200), and then such digital information may be stored in data registers (209) for reading out via the boundary-scan controller (1517).
摘要翻译：描述了用于为集成电路提供具有边界扫描的模拟能力的方法和装置。集成电路包括耦合到模拟 - 数字转换器（200）的边界扫描控制器（1517）。选择模拟通道用于输入到模数转换器（200）。模拟信息由模拟数字转换器（200）转换为数字信息，然后可以将数字信息存储在用于通过边界扫描控制器（1517）读出的数据寄存器（209）中。

2. 发明授权

US07966534B1 Identifying bitstream load issues in an integrated circuit 有权
标题翻译：识别集成电路中的位流负载问题
公开(公告)号：US07966534B1
公开(公告)日：2011-06-21
申请号：US12484150
申请日：2009-06-12
申请人： Neil G. Jacobson
发明人： Neil G. Jacobson
IPC分类号： G01R31/28 , G01R31/02 , G06F11/00 , H03K19/173 , H03K19/177
CPC分类号： G01R31/318516 , G06F11/0721 , G06F11/0757 , G06F11/0793 , G11C2029/0411
摘要： A method of detecting an error when loading a programmable integrated circuit (IC) can include detecting a predetermined bit pattern indicating a start of a bitstream within the programmable IC, starting a timer within the programmable IC responsive to detecting the predetermined bit pattern, and determining whether a bitstream load complete condition has occurred prior to expiration of the timer. When the timer expires prior to an occurrence of the bitstream load complete condition, at least one recovery action can be implemented.
摘要翻译：当加载可编程集成电路（IC）时检测错误的方法可以包括检测指示可编程IC内的比特流开始的预定位模式，响应于检测到预定位模式，启动可编程IC内的定时器，以及确定在定时器到期之前是否已经发生比特流加载完成条件。当定时器在比特流加载完成条件发生之前到期时，可以实现至少一个恢复动作。

3. 发明授权

US07913209B1 Determining a cycle basis of a directed graph 有权
标题翻译：确定有向图的周期基础
公开(公告)号：US07913209B1
公开(公告)日：2011-03-22
申请号：US12047663
申请日：2008-03-13
申请人： Kang Wu , Neil G. Jacobson
发明人： Kang Wu , Neil G. Jacobson
IPC分类号： G06F17/50 , G06F7/00
CPC分类号： G06F17/5045
摘要： A cycle basis is efficiently determined for a directed graph. A first depth-first search of the directed graph classifies each of the edges of the directed graph to have a type that is one of a within-tree type for an edge within a tree of the first depth first search, a forward type for an edge skipping forward along the tree, a back type for an edge directed back along the tree, or a cross type for an edge between two subtrees of the tree. A second depth-first search of the directed graph determines a respective cycle for each of the edges of the back type. A third depth-first search of the directed graph determines a respective cycle for each of the edges of the cross type that is included a cycle. The basis is output the basis that specifies each of the respective cycles.
摘要翻译：针对有向图有效地确定周期的基础。有向图的第一深度优先搜索将有向图的每个边缘分类为对于第一深度第一搜索的树中的边缘的树内类型之一的类型，对于边缘沿着树向前跳，沿着树向后指向的边的背面类型，或树的两个子树之间的边缘的交叉类型。有向图的第二深度优先搜索确定后面类型的每个边缘的相应周期。有向图的第三深度优先搜索确定包括循环的交叉类型的每个边缘的相应周期。基础是输出指定各个周期的基础。

4. 发明授权

US07363545B1 System and method for overcoming download cable bottlenecks during programming of integrated circuit devices 有权
标题翻译：在集成电路设备编程期间克服下载电缆瓶颈的系统和方法
公开(公告)号：US07363545B1
公开(公告)日：2008-04-22
申请号：US10162239
申请日：2002-06-03
申请人： Neil G. Jacobson , Emigdio M. Flores, Jr. , Sanjay Srivastava , Bin Dai , Sungnien Jerry Mao
发明人： Neil G. Jacobson , Emigdio M. Flores, Jr. , Sanjay Srivastava , Bin Dai , Sungnien Jerry Mao
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G06F11/267
摘要： A software architecture for facilitating communications between a computer or workstation and a programming apparatus used to program a PLD by minimizing the number of two-way communications on a standard download cable (e.g., RS232, USB) connected between the computer and the programming apparatus. A first component used to encode programming instructions and configuration data to form a first transmission stream that is transmitted to the programming apparatus in a single, long burst. The programming apparatus includes a second component of the software architecture that interprets the first transmission stream and programs the PLD using, for example, Boundary-Scan signals that are generated in response to the programming instructions and configuration data. A buffer memory stores data shifted out of the PLD during the programming operation, which is transmitted to the computer in a single, long burst after the first transmission stream is completed.
摘要翻译：一种用于促进计算机或工作站与用于通过连接在计算机和编程设备之间的标准下载电缆（例如，RS232，USB））上最小化双向通信数量来编程PLD的程序设备之间的通信的软件架构。用于编码编程指令和配置数据以形成以单个长突发发送到编程设备的第一传输流的第一组件。编程设备包括软件架构的第二组件，其解释第一传输流并且使用例如响应于编程指令和配置数据生成的边界扫描信号对PLD进行编程。缓冲存储器存储在编程操作期间从PLD移出的数据，其在第一传输流完成之后以单个长的突发发送到计算机。

5. 发明授权

US5784577A Automated control system for programming PLDs 失效
标题翻译：用于编程PLD的自动控制系统
公开(公告)号：US5784577A
公开(公告)日：1998-07-21
申请号：US699068
申请日：1996-08-05
申请人： Neil G. Jacobson , David Chiang
发明人： Neil G. Jacobson , David Chiang
IPC分类号： G06F1/00 , G06F12/14 , G06F21/00 , G11C16/22 , G06F13/10
CPC分类号： G06F21/76 , G06F12/1466 , G11C16/22 , G06F2207/7219
摘要： In an automated control system, a user must be authorized to modify the configuration data of a programmable logic device (PLD). After authorization is confirmed, the PLD is unlocked. Then, the configuration data of the PLD and the contents of a version control register are read back and archived, thereby providing a security back-up should the user need to retrieve the original data. After readback, the version control number is automatically incremented. This incremented version control number and the modified configuration data provided by the user are downloaded to the PLD. Finally, the PLD is locked.
摘要翻译：在自动控制系统中，用户必须被授权修改可编程逻辑器件（PLD）的配置数据。授权确认后，解锁PLD。然后，PLD的配置数据和版本控制寄存器的内容被回读和归档，从而在用户需要检索原始数据时提供安全备份。回读后，版本控制号自动递增。该增量的版本控制号码和由用户提供的修改的配置数据被下载到PLD。最后，PLD被锁定。

6. 发明授权

US07302562B1 Transmitting configuration data to a target programmable device after updating an intermediate programmable device 有权
标题翻译：在更新中间可编程设备后，将配置数据发送到目标可编程设备
公开(公告)号：US07302562B1
公开(公告)日：2007-11-27
申请号：US10981931
申请日：2004-11-05
申请人： Neil G. Jacobson , Emigdio M. Flores, Jr. , Sanjay Srivastava , Bin Dai , Sungnien Mao , Rosa M. Y. Chow , Pushpasheel Tawade , David E. Schweigler , Brian D. Erickson , Bernardo A. Elayda, III
发明人： Neil G. Jacobson , Emigdio M. Flores, Jr. , Sanjay Srivastava , Bin Dai , Sungnien Mao , Rosa M. Y. Chow , Pushpasheel Tawade , David E. Schweigler , Brian D. Erickson , Bernardo A. Elayda, III
IPC分类号： G06F7/38
CPC分类号： G06F8/65 , G06F8/654
摘要： Method and system for a programmable device programmer. The disclosure describes various embodiments for programming a target programmable device by a programmer. In one embodiment, the programmer determines availability of updated configuration data for a hardware component of the programmer. The programmer includes the software component coupled to the hardware component. An update mode of the hardware component is enabled in response to availability of the updated configuration data, and programming of the target programmable device is disabled while the hardware component is in the update mode. A programmable device internal to the hardware component is programmed with the updated configuration data while the hardware component is in the update mode, and the update mode is disabled in response to completion of programming of the at least one programmable device. A target programmable device may then be programmed by the programmer having the updated configuration data.
摘要翻译：可编程器件编程器的方法和系统。本公开描述了用于由程序员编程目标可编程器件的各种实施例。在一个实施例中，编程器确定用于编程器的硬件组件的更新的配置数据的可用性。程序员包括耦合到硬件组件的软件组件。响应于更新的配置数据的可用性，启用硬件组件的更新模式，并且当硬件组件处于更新模式时禁用目标可编程设备的编程。当硬件组件处于更新模式时，硬件组件内部的可编程设备被编程为更新的配置数据，并且响应于至少一个可编程设备的编程完成而禁用更新模式。然后可以由具有更新的配置数据的编程器对目标可编程设备进行编程。

7. 发明授权

US07091745B1 Indicating completion of configuration for programmable devices 有权
标题翻译：指示可编程器件的配置完成
公开(公告)号：US07091745B1
公开(公告)日：2006-08-15
申请号：US10853403
申请日：2004-05-24
申请人： Neil G. Jacobson
发明人： Neil G. Jacobson
IPC分类号： H03K19/177 , H01L25/00 , G06F7/38
CPC分类号： H03K19/17748 , H03K19/1776 , H03K19/17764
摘要： Various approaches for indicating completion of configuration of programmable logic devices are disclosed. In one embodiment, a plurality of configuration memory cells are arranged for storage of a configuration bitstream for implementing a circuit design on the programmable logic circuit. A plurality of configurable resources are coupled to the configuration memory cells, and each configurable resource implements a function based on data stored in one or more of the configuration memory cells coupled to the configurable resource. A logic circuit is coupled to a subset of the configuration memory cells and is configured to assert a done signal in response to states of the subset of the configuration memory cells.
摘要翻译：公开了用于指示可编程逻辑器件的配置完成的各种方法。在一个实施例中，布置多个配置存储器单元以存储用于在可编程逻辑电路上实现电路设计的配置位流。多个可配置资源耦合到配置存储器单元，并且每个可配置资源基于存储在耦合到可配置资源的一个或多个配置存储器单元中的数据来实现功能。逻辑电路耦合到配置存储器单元的子集，并且被配置为响应于配置存储器单元的子集的状态来断言完成信号。

8. 发明授权

US5999014A Method for concurrently programming or accessing a plurality of in-system-programmable logic devices 失效
标题翻译：用于同时编程或访问多个在系统可编程逻辑设备的方法
公开(公告)号：US5999014A
公开(公告)日：1999-12-07
申请号：US932307
申请日：1997-09-17
申请人： Neil G. Jacobson , Matthew T. Murphy
发明人： Neil G. Jacobson , Matthew T. Murphy
IPC分类号： G06F17/50 , G06F7/38 , H03K19/173 , H03K19/177
CPC分类号： G06F17/5054
摘要： An improved method for concurrently programming in-system programmable logic devices (PLDs). More specifically, where within a plurality of serially connected PLDs, there are devices having different numbers of programmable memory cells, and devices whose memory cells require different wait periods to carry out programming, the method herein provides more optimum time efficiency and uses significantly less time overall for programming, erasing or reading back the PLDs. Also, the invention accommodates the implementation of retries to assure complete programming or erasing even when the initial attempt is not entirely successful. The method provides steps for accommodating PLDs with different wait times by bypassing fully programmed devices and speeding up programming times after smaller and slower devices are programmed and larger and faster devices are still not fully programmed. The method employs the step of altering the program implementation from concurrent to sequential programming to optimize retry efficiency.
摘要翻译：一种用于同时编程系统可编程逻辑器件（PLD）的改进方法。更具体地说，在多个串行连接的PLD中，存在具有不同数量的可编程存储器单元的器件以及其存储器单元需要不同等待周期来执行编程的器件，本文中的方法提供更优化的时间效率并且使用明显更少的时间整体用于编程，擦除或读回PLD。此外，本发明适用于重试的实现，以确保即使初始尝试不完全成功也能完全编程或擦除。该方法提供了通过绕过完全编程的设备来容纳具有不同等待时间的PLD的步骤，并且在编程较小和较慢的设备之后加快编程时间，并且更大和更快的设备仍未被完全编程。该方法采用将程序实现从并发改为顺序编程的步骤，以优化重试效率。

9. 发明授权

US5694399A Processing unit for generating signals for communication with a test access port 失效
标题翻译：用于产生用于与测试访问端口通信的信号的处理单元
公开(公告)号：US5694399A
公开(公告)日：1997-12-02
申请号：US631766
申请日：1996-04-10
申请人： Neil G. Jacobson , Anthony S. Maraldo
发明人： Neil G. Jacobson , Anthony S. Maraldo
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318572
摘要： A system for interfacing with a test access communication port. Specifically, the present invention has application to the IEEE 1149.1 Test Access Port ("JTAG") standard. The novel system includes a hardware unit having a memory unit and a special processor unit (SPU) that interfaces between the test access port and components of a general purpose host computer system. The host computer system uses software procedures to formulate a set of compressed instructions instructing the hardware unit to generate and/or receive signals in connection with the test access port. In one embodiment, the host computer system contains configuration data in a special format. The host computer system translates this configuration data into the compressed instructions which are transmitted to the hardware unit causing it to download the configuration data using signals recognized by the test access port. The data is downloaded into a programmable integrated circuit device using the test access port. The SPU contains circuitry to expand the compressed instruction to generate the appropriate driving and receiving signals of the test access port. In one embodiment, clock, state machine, and data-in signals are generated by the SPU while a data-out signal can be received and relayed to the host computer system. The host computer system can be of a number of well known platforms (e.g., x86, DEC Alpha, Power PC, Mips, RISC, etc.).
摘要翻译：用于与测试访问通信端口进行接口的系统。具体地说，本发明适用于IEEE 1149.1测试接入端口（“JTAG”）标准。该新颖系统包括具有存储器单元和在测试访问端口和通用主机计算机系统的组件之间进行接口的特殊处理器单元（SPU）的硬件单元。主计算机系统使用软件程序来制定一组压缩指令，指示硬件单元产生和/或接收与测试访问端口相关的信号。在一个实施例中，主计算机系统包含特殊格式的配置数据。主计算机系统将该配置数据转换成被发送到硬件单元的压缩指令，使其使用由测试访问端口识别的信号来下载配置数据。使用测试访问端口将数据下载到可编程集成电路设备中。 SPU包含扩展压缩指令以产生测试访问端口的适当驱动和接收信号的电路。在一个实施例中，时钟，状态机和数据输入信号由SPU产生，同时可以接收数据输出信号并将其中继到主计算机系统。主计算机系统可以是许多众所周知的平台（例如，x86，DEC Alpha，Power PC，Mips，RISC等）。

10. 发明授权

US07610534B1 Determining a length of the instruction register of an unidentified device on a scan chain 有权
标题翻译：确定扫描链上未识别设备的指令寄存器的长度
公开(公告)号：US07610534B1
公开(公告)日：2009-10-27
申请号：US11725664
申请日：2007-03-20
申请人： Neil G. Jacobson
发明人： Neil G. Jacobson
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318552 , G01R31/318555 , G01R31/318558
摘要： Methods and systems are provided for determining a total length of instruction registers. A data shift of a scan chain determines whether each device in the scan chain is an identified device. An overall length of the instruction registers of the devices is determined from an instruction shift. An actual position is determined for an identified device between each pair of sub-sequences of unidentified devices. An instruction shift of the scan chain attempts to set the respective instruction register of the identified device using one or more trial positions. If a data shift of the scan chain obtains the recognized value of the respective identification register of the identified device for one of the trial positions, then this trial position is the actual position within the overall length. The total length is determined for the instruction registers of the unidentified devices in each sub-sequence of the unidentified devices.
摘要翻译：提供了用于确定指令寄存器总长度的方法和系统。扫描链的数据移位确定扫描链中的每个设备是否是识别的设备。根据指令移位确定设备的指令寄存器的总长度。确定在未识别设备的每对子序列之间的已识别设备的实际位置。扫描链的指令移位尝试使用一个或多个试用位置来设置所识别的设备的相应指令寄存器。如果扫描链的数据移位获得了针对一个试验位置的所识别的装置的相应识别寄存器的识别值，则该试验位置是整个长度内的实际位置。为未识别设备的每个子序列中的未识别设备的指令寄存器确定总长度。

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