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1. 发明授权

US06856542B2 Programmable logic device circuit and method of fabricating same 有权
标题翻译：可编程逻辑器件电路及其制造方法
公开(公告)号：US06856542B2
公开(公告)日：2005-02-15
申请号：US10164245
申请日：2002-06-04
申请人： Anirban Roy , Luca Giovanni Fasoli
发明人： Anirban Roy , Luca Giovanni Fasoli
IPC分类号： H01L21/82 , G11C14/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1736 , H01L27/115 , H01L27/11521 , H01L27/11803
摘要： A programmable logic device (PLD) and method for fabricating the PLD are disclosed. The PLD includes an array of PLD cells. Each PLD cell may include a programmable transistor and a select transistor. The PLD array is divided into at least one first area and at least one second area adjacent the at least one first area. The at least one first area includes the programmable transistors and the at least one second area includes the select transistors.
摘要翻译：公开了一种用于制造PLD的可编程逻辑器件（PLD）和方法。 PLD包括一系列PLD细胞。每个PLD单元可以包括可编程晶体管和选择晶体管。 PLD阵列被分成至少一个第一区域和与该至少一个第一区域相邻的至少一个第二区域。所述至少一个第一区域包括可编程晶体管，并且所述至少一个第二区域包括所述选择晶体管。

2. 发明授权

US06563732B2 Redundancy circuit and method for flash memory devices 有权
标题翻译：闪存设备的冗余电路和方法
公开(公告)号：US06563732B2
公开(公告)日：2003-05-13
申请号：US09922068
申请日：2001-08-02
申请人： Stella Matarrese , Luca Giovanni Fasoli
发明人： Stella Matarrese , Luca Giovanni Fasoli
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/81
摘要： A method and circuit are disclosed for replacing defective columns of flash memory cells in flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying at least one column of memory cells in any block of memory cells as being defective. The circuit further includes control circuitry for replacing an addressed column of memory cells with a redundant column of memory cells upon an affirmative determination that a set of storage elements identifies the addressed column of memory cells as being defective.
摘要翻译：公开了一种用于替换闪存装置中闪存单元的有缺陷的列的方法和电路。电路包括多组存储元件，每组存储元件能够将存储器单元的任何块中的至少一列存储器单元识别为有缺陷的。电路还包括控制电路，用于在肯定地确定一组存储元件将存储器单元的寻址列识别为有缺陷的情况下，用冗余列的存储器单元替换存储器单元的列。

3. 发明授权

US06490197B1 Sector protection circuit and method for flash memory devices 有权
标题翻译：闪存器件的扇区保护电路和方法
公开(公告)号：US06490197B1
公开(公告)日：2002-12-03
申请号：US09922043
申请日：2001-08-02
申请人： Luca Giovanni Fasoli
发明人： Luca Giovanni Fasoli
IPC分类号： G11C1604
CPC分类号： G11C16/22 , G11C11/56
摘要： A method and circuit are disclosed for providing sector protection to sectors of nonvolatile memory cells in a nonvolatile memory device. The circuit includes maintaining sector protection information in the core of memory cells in the nonvolatile memory device. In this way, the circuitry and/or algorithms utilized for reading and modifying memory cells in the memory cell core that maintain the sector protection information is the same utilized for reading and modifying the other memory cells in the core.
摘要翻译：公开了一种用于向非易失性存储器件中的非易失性存储器单元的扇区提供扇区保护的方法和电路。该电路包括在非易失性存储器件中的存储器单元的核心中维护扇区保护信息。以这种方式，用于读取和修改存储器单元核心中保持扇区保护信息的存储单元的电路和/或算法与用于读取和修改核心中的其它存储单元相同。

4. 发明授权

US06552935B2 Dual bank flash memory device and method 有权
标题翻译：双银行闪存设备及方法
公开(公告)号：US06552935B2
公开(公告)日：2003-04-22
申请号：US09922044
申请日：2001-08-02
申请人： Luca Giovanni Fasoli
发明人： Luca Giovanni Fasoli
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C16/26 , G11C2216/22
摘要： A user configurable dual bank memory device is disclosed. The memory device includes a plurality of core banks of memory cells and a set of storage elements having stored therein configuration information. The configuration may be used to configure or group core banks of memory cells together to form a dual bank memory device. The memory device includes control circuitry for preventing a memory read operation from being completed in a core bank or user-configured dual bank in which an ongoing memory modify (program or erase) operation is being performed. The memory device further includes a first set of sense amplifiers dedicated to performing sense amplification only during memory read operations, and a second set of sense amplifiers dedicated to performing sense amplification only during memory modify operations.
摘要翻译：公开了一种用户可配置双组存储器件。存储器件包括存储器单元的多个核心组和存储有配置信息的一组存储元件。该配置可以用于将存储器单元的核心组配置或分组在一起以形成双组存储器设备。存储器件包括控制电路，用于防止存储器读取操作在核心存储体或用户配置的双组中完成，其中正在进行存储器修改（编程或擦除）操作。存储器件还包括专用于仅在存储器读取操作期间执行读出放大的第一组读出放大器，以及仅在存储器修改操作期间专用于执行读出放大的第二组读出放大器。

5. 发明授权

US06594177B2 Redundancy circuit and method for replacing defective memory cells in a flash memory device 有权
标题翻译：用于替换闪存设备中的有缺陷的存储单元的冗余电路和方法
公开(公告)号：US06594177B2
公开(公告)日：2003-07-15
申请号：US09922176
申请日：2001-08-02
申请人： Stella Matarrese , Luca Giovanni Fasoli
发明人： Stella Matarrese , Luca Giovanni Fasoli
IPC分类号： G11C1604
CPC分类号： G11C29/808 , G11C29/81
摘要： A method and circuit are disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying a single addressed column of memory cells is to be replaced or a main column line and regular columns of memory cells associated therewith to be replaced. In the event a main column line and the associated regular columns are identified for replacement by a set of storage elements, the set additionally indicates whether the regular columns are regular columns in a single block of memory cells or multiple blocks. Redundancy circuitry performs the replacement operation during a memory access operation based upon the information stored in the sets of storage elements.
摘要翻译：公开了一种用于替换闪存器件中闪存单元的有缺陷的列的方法和电路。该电路包括多组存储元件，能够识别存储器单元的单个寻址列的每组存储元件将被替换，或者主列线和与其相关联的常规列的存储器单元被替换。在主列线和关联的常规列被识别用于由一组存储元件替换的情况下，该集合另外指示常规列是单个存储器单元块还是多个块中的常规列。冗余电路基于存储在存储元件组中的信息在存储器访问操作期间执行替换操作。

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