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1. 发明授权

US09347835B2 Systems and methods for peak junction temperature sensing and thermal safe operating area protection 有权
标题翻译：峰值结温检测和热安全操作区保护的系统和方法
公开(公告)号：US09347835B2
公开(公告)日：2016-05-24
申请号：US13563484
申请日：2012-07-31
申请人： Anindya Bhattacharya , Tim Green , Jing Bai
发明人： Anindya Bhattacharya , Tim Green , Jing Bai
IPC分类号： G01K3/00 , G01K3/10 , G01K7/42
CPC分类号： G01K3/10 , G01K3/02 , G01K7/427
摘要： A peak junction temperature monitoring system for a semiconductor device includes a peak power dissipation sensor for sensing the peak power dissipation in the device. A temperature sensor senses an average temperature of the device, and a peak junction temperature computation circuit generates a signal representative of a peak junction temperature based on input from the peak power dissipation sensor and the temperature sensor.
摘要翻译：用于半导体器件的峰值结温监测系统包括峰值功耗传感器，用于感测器件中的峰值功耗。温度传感器感测器件的平均温度，并且峰值结温度计算电路基于来自峰值功耗传感器和温度传感器的输入产生表示峰值结温的信号。

2. 发明申请

US20130044786A1 SYSTEMS AND METHODS FOR PEAK JUNCTION TEMPERATURE SENSING AND THERMAL SAFE OPERATING AREA PROTECTION 有权
标题翻译：峰值温度传感和热安全操作区域保护的系统和方法
公开(公告)号：US20130044786A1
公开(公告)日：2013-02-21
申请号：US13563484
申请日：2012-07-31
申请人： Anindya Bhattacharya , Tim Green , Jing Bai
发明人： Anindya Bhattacharya , Tim Green , Jing Bai
IPC分类号： G01K3/00
CPC分类号： G01K3/10 , G01K3/02 , G01K7/427
摘要： A peak junction temperature monitoring system for a semiconductor device includes a peak power dissipation sensor for sensing the peak power dissipation in the device. A temperature sensor senses an average temperature of the device, and a peak junction temperature computation circuit generates a signal representative of a peak junction temperature based on input from the peak power dissipation sensor and the temperature sensor.
摘要翻译：用于半导体器件的峰值结温监测系统包括峰值功耗传感器，用于感测器件中的峰值功耗。温度传感器感测器件的平均温度，并且峰值结温度计算电路基于来自峰值功耗传感器和温度传感器的输入产生表示峰值结温的信号。

3. 发明申请

US20070022070A1 Forgetful logic for artificial neural networks 审中-公开
标题翻译：人工神经网络的遗忘逻辑
公开(公告)号：US20070022070A1
公开(公告)日：2007-01-25
申请号：US11376382
申请日：2006-03-15
申请人： Richard Wells , David Cox , Anindya Bhattacharya
发明人： Richard Wells , David Cox , Anindya Bhattacharya
IPC分类号： G06N3/00 , G06F15/18 , G06J1/00
CPC分类号： G06N3/049 , G06N3/063
摘要： An embodiment includes a plurality of tangible electronic elements interconnected to form a forgetful latch. The forgetful latch includes a pass element operable to receive input pulses; a biasing element coupled to the pass element and operable to bias a storage node charged by at least one of the input pulses; and an inverter coupled to the biasing elements and operable to produce an output pulse that stretches the input pulses.
摘要翻译：一个实施例包括互连以形成健忘锁定器的多个有形电子元件。忘记的锁存器包括可操作以接收输入脉冲的通过元件; 偏置元件，其耦合到所述通过元件并且可操作以偏置由所述输入脉冲中的至少一个充电的存储节点; 以及反相器，其耦合到所述偏置元件并且可操作以产生延伸所述输入脉冲的输出脉冲。

4. 发明申请

US20090237163A1 TRIMMING TECHNIQUE FOR HIGH VOLTAGE AMPLIFIERS USING FLOATING LOW VOLTAGE STRUCTURES 有权
标题翻译：使用浮动低电压结构的高压放大器的调试技术
公开(公告)号：US20090237163A1
公开(公告)日：2009-09-24
申请号：US12053534
申请日：2008-03-21
申请人： Anindya Bhattacharya , David F. Cox
发明人： Anindya Bhattacharya , David F. Cox
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/72 , H03F2203/45318 , H03F2203/45352 , H03F2203/45371 , H03F2203/45646 , H03F2203/45674 , H03F2203/7236
摘要： The system contains a first MOS transistor having a first source element, a first drain element, and a first gate element. A first low voltage current source has two ends. The ends of the low voltage current source are connected to at least two of the first MOS transistor elements. At least one first Zener clamp is in parallel with the low voltage current source.
摘要翻译：该系统包含具有第一源极元件，第一漏极元件和第一栅极元件的第一MOS晶体管。第一低电压电流源有两端。低电压电流源的端部连接到至少两个第一MOS晶体管元件。至少一个第一齐纳钳位与低电压电流源并联。

5. 发明申请

US20070216483A1 Differential amplifier stage 有权
标题翻译：差分放大器级
公开(公告)号：US20070216483A1
公开(公告)日：2007-09-20
申请号：US11389574
申请日：2006-03-15
申请人： Anindya Bhattacharya , David Cox
发明人： Anindya Bhattacharya , David Cox
IPC分类号： H03F3/45
CPC分类号： H03F3/3069 , H03F1/0205 , H03F3/45179 , H03F2200/513 , H03F2203/45094 , H03F2203/45248 , H03F2203/45318 , H03F2203/45366 , H03F2203/45508 , H03F2203/45644 , H03F2203/45651 , H03F2203/45654
摘要： A differential amplifier stage includes one active load circuit connected to a pair of cross-coupled transistors that produce a differential signal. The active load circuit controls the rise time of the differential signal. The differential amplifier stage also includes another active load circuit connected to the pair of cross-coupled transistors. The second active load circuit controls the fall time of the differential signal.
摘要翻译：差分放大器级包括连接到产生差分信号的一对交叉耦合晶体管的一个有源负载电路。有源负载电路控制差分信号的上升时间。差分放大器级还包括连接到该对交叉耦合晶体管的另一有源负载电路。第二个有源负载电路控制差分信号的下降时间。

6. 发明授权

US08421540B1 Method and apparatus for run-time short circuit protection for amplifiers 有权
标题翻译：用于放大器运行时短路保护的方法和装置
公开(公告)号：US08421540B1
公开(公告)日：2013-04-16
申请号：US13155100
申请日：2011-06-07
申请人： Anindya Bhattacharya
发明人： Anindya Bhattacharya
IPC分类号： H02H7/20
CPC分类号： H03F1/52 , H03F3/185 , H03F3/21 , H03F2200/03
摘要： The system contains a first input receiving a signal from the amplifier input. A second input receives a signal from the amplifier output. A gain modification device is connected to the second input thereby reducing an amplitude of the signal from the amplifier output. A difference element connected to the gain modification device and the first input subtracts one of the first input and the second input from the other of the first input and the second input and outputting a difference voltage. A comparator, connected to the difference element and a threshold voltage source, compares the difference voltage to a threshold voltage. A disabling device is connected to the comparator and an output stage of the amplifier, wherein an output stage of the amplifier is disabled when the threshold voltage exceeds the difference voltage.
摘要翻译：该系统包含接收来自放大器输入端的信号的第一输入端。第二输入接收来自放大器输出的信号。增益修改装置连接到第二输入，从而减小来自放大器输出的信号的幅度。连接到增益修改装置和第一输入的差分元件从第一输入和第二输入中的另一个中减去第一输入和第二输入中的一个，并输出差分电压。连接到差分元件和阈值电压源的比较器将差分电压与阈值电压进行比较。禁用装置连接到比较器和放大器的输出级，其中当阈值电压超过差分电压时，放大器的输出级被禁止。

7. 发明授权

US08575975B1 Stepped voltage drive for driving capacitive loads 有权
标题翻译：用于驱动电容性负载的步进电压驱动
公开(公告)号：US08575975B1
公开(公告)日：2013-11-05
申请号：US12571352
申请日：2009-09-30
申请人： Anindya Bhattacharya , John Melanson
发明人： Anindya Bhattacharya , John Melanson
IPC分类号： H03K4/02 , H02M3/18 , B41J29/38
CPC分类号： B41J2/04541 , B41J2/04548 , B41J2/0455 , B41J2/04581 , H03K4/063 , H03K5/12
摘要： A system and method for charging heavy capacitive loads may comprise an n-stage stacked charging circuit wherein n is an integer greater than one which may comprise n−1 capacitors and a voltage supply, each sequentially electrically connected to the capacitive load in an order through a respective first through nth switch during a respective first through nth charging time period; the n−1th capacitors each sequentially electrically connected to the capacitive load in reverse order during a first through n−1th discharging time period through the respective n−1th through first switches. The system and method may comprise an n+1th switch electrically connecting the capacitive load to ground during an nth discharging period. The capacitive load may comprise a piezoelectric element, which may comprise an inkjet printer head inkjet actuator.
摘要翻译：用于对高容性负载充电的系统和方法可以包括n级堆叠充电电路，其中n是大于1的整数，其可以包括n-1个电容器和电压源，每个电容器和电压源按顺序电连接到电容负载，顺序通过在相应的第一至第n充电时间段期间相应的第一至第N开关; 在第一到第n-1放电时间段期间，第n-1个电容器通过相应的第n-1个至第一开关以相反顺序电连接到电容性负载。该系统和方法可以包括在第n个放电周期期间将电容性负载电连接到地的第n + 1开关。电容性负载可以包括压电元件，其可以包括喷墨打印头喷墨致动器。

8. 发明授权

US08324943B1 High voltage linear amplifier driving heavy capacitive loads with reduced power dissipation 有权
标题翻译：高电压线性放大器驱动大容量负载，降低功耗
公开(公告)号：US08324943B1
公开(公告)日：2012-12-04
申请号：US12571340
申请日：2009-09-30
申请人： Anindya Bhattacharya , John Melanson
发明人： Anindya Bhattacharya , John Melanson
IPC分类号： H03K5/12 , H03K17/04 , B41J29/38
CPC分类号： B41J2/04541 , B41J2/04548 , B41J2/0455 , B41J2/04581 , H03K4/063 , H03K5/12
摘要： A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.
摘要翻译：容性负载驱动电路可以包括高电流驱动放大器，其被配置为在跨过容性负载的电压的高电流斜坡上升到截止电压时耦合到电容性负载; 低电流驱动放大器被配置为在跨过容性负载的电压的低电流斜升期间从截止电压到跨过容性负载的最大电压连接到电容性负载; 以及高电流驱动放大器，被配置为在跨过容性负载的电压的高电流斜降期间连接到电容性负载。在电容负载两端的电压稳定期间，低电流驱动放大器可以连接到电容性负载，低电平斜坡上升和高电流斜坡下降。

9. 发明授权

US07786799B2 Trimming technique for high voltage amplifiers using floating low voltage structures 有权
标题翻译：使用浮动低电压结构的高压放大器的微调技术
公开(公告)号：US07786799B2
公开(公告)日：2010-08-31
申请号：US12053534
申请日：2008-03-21
申请人： Anindya Bhattacharya , David F. Cox
发明人： Anindya Bhattacharya , David F. Cox
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/72 , H03F2203/45318 , H03F2203/45352 , H03F2203/45371 , H03F2203/45646 , H03F2203/45674 , H03F2203/7236
摘要： The system contains a first MOS transistor having a first source element, a first drain element, and a first gate element. A first low voltage current source has two ends. The ends of the low voltage current source are connected to at least two of the first MOS transistor elements. At least one first Zener clamp is in parallel with the low voltage current source.
摘要翻译：该系统包含具有第一源极元件，第一漏极元件和第一栅极元件的第一MOS晶体管。第一低电压电流源有两端。低电压电流源的端部连接到至少两个第一MOS晶体管元件。至少一个第一齐纳钳位与低电压电流源并联。

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