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1. 发明申请

US20130268619A1 SERVER INCLUDING SWITCH CIRCUITRY 有权
标题翻译：服务器包括开关电路
公开(公告)号：US20130268619A1
公开(公告)日：2013-10-10
申请号：US13995231
申请日：2011-12-01
申请人： Anil Vasudevan , Parthasarathy Sarangam , Ilango S. Ganga
发明人： Anil Vasudevan , Parthasarathy Sarangam , Ilango S. Ganga
IPC分类号： H04L12/24
CPC分类号： H04L41/04 , G06F13/385
摘要： An embodiment may include at least one server processor that may control, at least in part, server switch circuitry data and control plane processing. The at least one processor may include at least one cache memory that is capable of being involved in at least one data transfer that involves at least one component of the server. The at least one data transfer may be carried out in a manner that by-passes involvement of server system memory. The switch circuitry may be communicatively coupled to the at least one processor and to at least one node via communication links. The at least one processor may select, at least in part, at least one communication protocol to be used by the links. The switch circuitry may forward, at least in part, via at least one of the links at least one received packet. Many modifications are possible.
摘要翻译：一个实施例可以包括至少一个可以至少部分地控制服务器交换机电路数据和控制平面处理的服务器处理器。所述至少一个处理器可以包括至少一个高速缓存存储器，其能够涉及涉及服务器的至少一个组件的至少一个数据传输。所述至少一个数据传送可以以服务器系统存储器的旁路方式进行。开关电路可以经由通信链路通信地耦合到至少一个处理器和至少一个节点。至少一个处理器可以至少部分地选择要由链路使用的至少一个通信协议。交换机电路可以至少部分地经由至少一个链路至少一个接收的分组转发。许多修改是可能的。

2. 发明授权

US09736011B2 Server including switch circuitry 有权
公开(公告)号：US09736011B2
公开(公告)日：2017-08-15
申请号：US13995231
申请日：2011-12-01
申请人： Anil Vasudevan , Parthasarathy Sarangam , Ilango S. Ganga
发明人： Anil Vasudevan , Parthasarathy Sarangam , Ilango S. Ganga
IPC分类号： G06F15/167 , H04L12/24 , G06F13/38
CPC分类号： H04L41/04 , G06F13/385
摘要： An embodiment may include at least one server processor that may control, at least in part, server switch circuitry data and control plane processing. The at least one processor may include at least one cache memory that is capable of being involved in at least one data transfer that involves at least one component of the server. The at least one data transfer may be carried out in a manner that by-passes involvement of server system memory. The switch circuitry may be communicatively coupled to the at least one processor and to at least one node via communication links. The at least one processor may select, at least in part, at least one communication protocol to be used by the links. The switch circuitry may forward, at least in part, via at least one of the links at least one received packet. Many modifications are possible.

3. 发明授权

US07987307B2 Interrupt coalescing control scheme 有权
标题翻译：中断合并控制方案
公开(公告)号：US07987307B2
公开(公告)日：2011-07-26
申请号：US11525738
申请日：2006-09-22
申请人： Parthasarathy Sarangam , Anil Vasudevan
发明人： Parthasarathy Sarangam , Anil Vasudevan
IPC分类号： G06F13/24 , G06F13/32
CPC分类号： G06F13/26
摘要： In an embodiment, a method is provided. The method of this embodiment provides determining a flow context associated with a receive packet; and if the flow context complies with a dynamic interrupt moderation policy having one or more rules, generating an interrupt to process the receive packet substantially independently of an interrupt generated in accordance with an interrupt coalescing scheme (“coalesced interrupt”). Other embodiments are disclosed and/or claimed.
摘要翻译：在一个实施例中，提供了一种方法。该实施例的方法提供确定与接收分组相关联的流上下文; 并且如果流上下文符合具有一个或多个规则的动态中断调节策略，则生成中断以基本上独立于根据中断聚合方案（“合并中断”）生成的中断来处理接收分组。披露和/或要求保护的其它实施例。

4. 发明授权

US09009367B2 Adaptive interrupt moderation 有权
标题翻译：自适应中断节制
公开(公告)号：US09009367B2
公开(公告)日：2015-04-14
申请号：US13566298
申请日：2012-08-03
申请人： Yadong Li , Linden Cornett , Manasi Deval , Anil Vasudevan , Parthasarathy Sarangam
发明人： Yadong Li , Linden Cornett , Manasi Deval , Anil Vasudevan , Parthasarathy Sarangam
IPC分类号： G06F3/00 , G06F15/16 , G06F13/24
CPC分类号： G06F13/24 , H04L69/165
摘要： Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.
摘要翻译：通常，本公开涉及自适应中断调节。方法可以包括：至少部分地基于与每个连接相关联的连接标识符，由主机设备确定主机设备与一个或多个链路伙伴之间的连接数; 由所述主机设备至少部分地基于多个连接来确定新的中断率; 通过所述主机设备更新具有与所述新中断速率相关的值的中断调节定时器; 并配置中断调节定时器以允许以新的中断速率发生中断。

5. 发明申请

US20070156960A1 Ordered combination of uncacheable writes 审中-公开
标题翻译：有序的不可写入的组合
公开(公告)号：US20070156960A1
公开(公告)日：2007-07-05
申请号：US11323793
申请日：2005-12-30
申请人： Anil Vasudevan , Parthasarathy Sarangam , Sujoy Sen
发明人： Anil Vasudevan , Parthasarathy Sarangam , Sujoy Sen
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： Methods and apparatus to reduce the number of uncacheable write requests are described. In one embodiment, a single uncacheable write request is sent instead of a plurality of uncacheable write requests to an address.
摘要翻译：描述减少不可写入写入请求数量的方法和装置。在一个实施例中，单个不可缓存的写入请求被发送而不是多个不可缓存的写入请求到地址。

6. 发明申请

US20150319250A1 TECHNOLOGIES FOR ACCELERATING NETWORK VIRTUALIZATION 审中-公开
标题翻译：加速网络虚拟化的技术
公开(公告)号：US20150319250A1
公开(公告)日：2015-11-05
申请号：US14583667
申请日：2014-12-27
申请人： Anil Vasudevan , Parthasarathy Sarangam , Rajesh M. Sankaran
发明人： Anil Vasudevan , Parthasarathy Sarangam , Rajesh M. Sankaran
IPC分类号： H04L29/08 , H04L12/24 , H04L12/46
CPC分类号： H04L67/10 , H04L12/4633 , H04L41/5054 , H04L67/141
摘要： Technologies for accelerated network virtualization include executing packet processing functions by a network virtualizer established in a provider partition of a computing device and offloading packet movement functions to a network interface controller of the computing device. In the illustrative embodiments, the network interface controller includes one or more tenant-facing ports, a provider-facing port, and an external network-facing port, which are used by the network interface controller to receive, send, and pass packets from, to, and between the various partitions of the computing device. To transmit a packet, the network virtualizer generates a provider header, and either the network virtualizer or the network interface controller encapsulates a packet received from the tenant partition with the provider header. To receive a packet, either the network virtualizer or the network interface controller strips a provider header from the received packet.
摘要翻译：用于加速网络虚拟化的技术包括通过在计算设备的提供商分区中建立的网络虚拟器执行分组处理功能，并且将分组移动功能卸载到计算设备的网络接口控制器。在说明性实施例中，网络接口控制器包括一个或多个面向租户的端口，面向提供者的端口和外部网络面向端口，由网络接口控制器用于接收，发送和传递分组，到计算设备的各个分区之间和之间。为了传输分组，网络虚拟器生成提供者头部，并且网络虚拟器或网络接口控制器将从租户分区接收的分组封装到提供商头部。为了接收分组，网络虚拟器或网络接口控制器从接收到的分组中剥离提供商头部。

7. 发明申请

US20140040514A1 ADAPTIVE INTERRUPT MODERATION 有权
标题翻译：自适应中断调制
公开(公告)号：US20140040514A1
公开(公告)日：2014-02-06
申请号：US13566298
申请日：2012-08-03
申请人： Yadong Li , Linden Cornett , Manasi Deval , Anil Vasudevan , Parthasarathy Sarangam
发明人： Yadong Li , Linden Cornett , Manasi Deval , Anil Vasudevan , Parthasarathy Sarangam
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , H04L69/165
摘要： Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.
摘要翻译：通常，本公开涉及自适应中断调节。方法可以包括：至少部分地基于与每个连接相关联的连接标识符，由主机设备确定主机设备与一个或多个链路伙伴之间的连接数; 由所述主机设备至少部分地基于多个连接来确定新的中断率; 通过所述主机设备更新具有与所述新中断速率相关的值的中断调节定时器; 并配置中断调节定时器以允许以新的中断速率发生中断。

8. 发明授权

US07206833B1 Platform independent alert detection and management 有权
标题翻译：平台独立的警报检测和管理
公开(公告)号：US07206833B1
公开(公告)日：2007-04-17
申请号：US09410483
申请日：1999-09-30
申请人： Parthasarathy Sarangam , Anil Vasudevan
发明人： Parthasarathy Sarangam , Anil Vasudevan
IPC分类号： G06F15/173
CPC分类号： H04L41/06 , H04L41/0213 , H04L41/0226
摘要： Platform independent alert detection and management. A software-based intermediary referred to herein as an alert proxy is used to transform binary, device-specific event or alert data into user-friendly plain text explanations of the event. A management device containing the alert proxy is able to return a contextually correct description of the event to an administrator or other interested party based upon the characteristics of the specific device initiating the event. Event data may be generated by alert software executing on an alert-enabled managed client or by alert hardware embodied within an alert-enabled managed client.
摘要翻译：平台独立的警报检测和管理。此处称为警报代理的基于软件的中介器用于将二进制特定于设备的事件或警报数据转换为用户友好的明文说明。包含警报代理的管理设备能够基于发起事件的特定设备的特性向管理员或其他感兴趣的方返回事件的上下文正确的描述。事件数据可以由在启用警报的受管客户端上执行的警报软件或者启用了启用警报的受管客户端内的警报硬件生成。

9. 发明申请

US20200183732A1 EFFICIENT RECEIVE INTERRUPT SIGNALING 审中-公开
公开(公告)号：US20200183732A1
公开(公告)日：2020-06-11
申请号：US16710556
申请日：2019-12-11
申请人： Linden Cornett , Anil Vasudevan , Parthasarathy Sarangam , Kiran Patil
发明人： Linden Cornett , Anil Vasudevan , Parthasarathy Sarangam , Kiran Patil
IPC分类号： G06F9/48 , G06F9/50
摘要： Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located. After asserting an interrupt, an RX queue may be auto-masked to prevent generation of additional events when new descriptors are enqueued in the RX queue.

10. 发明申请

US20080077724A1 Interrupt coalescing control scheme 有权
标题翻译：中断合并控制方案
公开(公告)号：US20080077724A1
公开(公告)日：2008-03-27
申请号：US11525738
申请日：2006-09-22
申请人： Parthasarathy Sarangam , Anil Vasudevan
发明人： Parthasarathy Sarangam , Anil Vasudevan
IPC分类号： G06F13/26
CPC分类号： G06F13/26
摘要： In an embodiment, a method is provided. The method of this embodiment provides determining a flow context associated with a receive packet; and if the flow context complies with a dynamic interrupt moderation policy having one or more rules, generating an interrupt to process the receive packet substantially independently of an interrupt generated in accordance with an interrupt coalescing scheme (“coalesced interrupt”). Other embodiments are disclosed and/or claimed.
摘要翻译：在一个实施例中，提供了一种方法。该实施例的方法提供确定与接收分组相关联的流上下文; 并且如果流上下文符合具有一个或多个规则的动态中断调节策略，则生成中断以基本上独立于根据中断聚合方案（“合并中断”）生成的中断来处理接收分组。披露和/或要求保护的其它实施例。

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