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1. 发明授权

US06461923B1 Sidewall spacer etch process for improved silicide formation 失效
标题翻译：用于改善硅化物形成的侧壁间隔蚀刻工艺
公开(公告)号：US06461923B1
公开(公告)日：2002-10-08
申请号：US09639816
申请日：2000-08-17
申请人： Angela T. Hui , Paul R. Besser , Susan H. Chen
发明人： Angela T. Hui , Paul R. Besser , Susan H. Chen
IPC分类号： H01L21336
CPC分类号： H01L21/2652 , H01L21/28518 , H01L29/665 , H01L29/6659
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein silicon substrate surfaces intended to be subjected to ion implantation for source/drain formation are protected from damage resulting from reactive plasma etching of a blanket insulative layer for sidewall spacer formation by leaving a residual thickness of the insulative layer thereon. The residual layer is retained during ion implantation and removed prior to salicide processing to provide an undamaged surface for optimal contact formation thereon. Embodiments include anisotropically plasma etching a major amount of the thickness of the blanket insulative layer during a preselected interval for sidewall spacer formation and removing the residual thickness thereof after source/drain implantation by etching with dilute aqueous HF.
摘要翻译：通过自对准硅化物工艺形成具有减小的或最小的结漏电的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中旨在进行用于源极/漏极形成的离子注入的硅衬底表面被保护免受由通过在其上留下绝缘层的剩余厚度来进行用于侧壁间隔物形成的覆盖绝缘层的反应等离子体蚀刻。残留层在离子注入期间被保留，并且在自对准硅化物处理之前被去除以提供未损坏的表面以在其上形成最佳的接触形成。实施例包括在用于侧壁间隔物形成的预选间隔期间各向异性等离子体蚀刻绝缘层的厚度的主要量，并且通过用稀HF水溶液蚀刻去除其源极/漏极注入之后的剩余厚度。

2. 发明授权

US06171919B2 MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation 有权
标题翻译： MOS晶体管形成工艺包括用于改善硅化物形成的后间隔蚀刻表面处理
公开(公告)号：US06171919B2
公开(公告)日：2001-01-09
申请号：US09361155
申请日：1999-07-27
申请人： Paul R. Besser , Minh Van Ngo , Simon S. Chan , Angela T. Hui
发明人： Paul R. Besser , Minh Van Ngo , Simon S. Chan , Angela T. Hui
IPC分类号： H01L21336
CPC分类号： H01L29/665
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.
摘要翻译：通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣。实施例包括通过进行氢离子等离子体处理来除去碳质残渣。

3. 发明授权

US06204136B1 Post-spacer etch surface treatment for improved silicide formation 有权
标题翻译：间隔后蚀刻表面处理以改善硅化物形成
公开(公告)号：US06204136B1
公开(公告)日：2001-03-20
申请号：US09386466
申请日：1999-08-31
申请人： Simon S. Chan , Minh Van Ngo , Paul R. Besser , Angela T. Hui
发明人： Simon S. Chan , Minh Van Ngo , Paul R. Besser , Angela T. Hui
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/31116
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.
摘要翻译：通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣。实施方案包括通过进行氢离子等离子体处理来除去碳质残渣。

4. 发明申请

US20080153224A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 审中-公开
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080153224A1
公开(公告)日：2008-06-26
申请号：US11735229
申请日：2007-04-13
申请人： Connie Pin Chin Wang , Simon Siu-Sing Chan , Angela T. Hui , Paul R. Besser , Shenqing Fang
发明人： Connie Pin Chin Wang , Simon Siu-Sing Chan , Angela T. Hui , Paul R. Besser , Shenqing Fang
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： An integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a contact on the outer doped region, thinning the contact for forming a thinned contact, and forming a metal plug on the thinned contact.
摘要翻译：提供了一种集成电路系统，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在外部掺杂区域上形成接触，减少接触以形成变薄的接触，以及在变薄的触点上形成金属插头。

5. 发明授权

US08790530B2 Planar cell ONO cut using in-situ polymer deposition and etch 有权
标题翻译：使用原位聚合物沉积和蚀刻的平面细胞ONO切割
公开(公告)号：US08790530B2
公开(公告)日：2014-07-29
申请号：US12703586
申请日：2010-02-10
申请人： Angela T. Hui , Gang Xue
发明人： Angela T. Hui , Gang Xue
IPC分类号： G01L21/30 , H01L21/302
CPC分类号： H01L27/11568 , H01L27/11565
摘要： A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.
摘要翻译：提供了一种电荷存储层分离的方法和制造方法。诸如聚合物层的层沉积在ONO层的顶部上，使得聚合物层被平坦化或近似平坦化。 ONO包括至少第一区域和第二区域，其中第一区域高于第二区域。例如，第一区域可以是在源极/漏极区域上的ONO的部分，并且第二区域可以是在浅沟槽上的ONO的部分。在聚合物层上进行蚀刻以暴露ONO层的第一区域，留下ONO的第二区域未曝光。蚀刻继续发生以蚀刻在第一区域处的暴露的ONO，使得ONO层在第一区域被蚀刻掉，并且第二区域保持未曝光。

6. 发明授权

US08349685B2 Dual spacer formation in flash memory 有权
标题翻译：闪存中的双间隔物形成
公开(公告)号：US08349685B2
公开(公告)日：2013-01-08
申请号：US12960437
申请日：2010-12-03
申请人： Angela T. Hui , Shenqing Fang
发明人： Angela T. Hui , Shenqing Fang
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L27/1157
摘要： A method and manufacture for memory device fabrication is provided. In one embodiment, at least one oxide-nitride spacer is formed as follows. An oxide layer is deposited over a flash memory device such that the deposited oxide layer is at least 250 Angstroms thick. The flash memory device includes a substrate and dense array of word line gates with gaps between each of the word lines gate in the dense array. Also, the deposited oxide layer is deposited such that it completely gap-fills the gaps between the word line gates of the dense array of word line gates. Next, a nitride layer is depositing over the oxide layer. Then, the nitride layer is etched until the at least a portion of the oxide layer is exposed. Next, the oxide layer is etched until at least a portion of the substrate is exposed.
摘要翻译：提供了一种用于存储器件制造的方法和制造。在一个实施方案中，如下形成至少一种氧化物 - 氮化物间隔物。氧化物层沉积在闪速存储器件上，使得沉积的氧化物层的厚度至少为250埃。闪速存储器件包括基板和密集阵列的字线栅极，在密集阵列中的每个字线栅极之间具有间隙。此外，沉积的氧化物层被沉积，使得其完全间隙地填充字线门的密集阵列的字线栅极之间的间隙。接下来，在氧化物层上沉积氮化物层。然后，蚀刻氮化物层直到暴露出氧化物层的至少一部分。接下来，蚀刻氧化物层直到基板的至少一部分露出。

7. 发明授权

US07985687B1 System and method for improving reliability in a semiconductor device 有权
标题翻译：用于提高半导体器件的可靠性的系统和方法
公开(公告)号：US07985687B1
公开(公告)日：2011-07-26
申请号：US11186969
申请日：2005-07-22
申请人： Angela T. Hui , Hiroyuki Kinoshita , Unsoon Kim , Harpreet K. Sachar
发明人： Angela T. Hui , Hiroyuki Kinoshita , Unsoon Kim , Harpreet K. Sachar
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/28273 , H01L21/28282 , H01L21/3081 , H01L21/31111 , H01L21/76232 , H01L27/11521 , H01L27/11568
摘要： A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.
摘要翻译：一种用于形成存储器件的方法包括在衬底上形成硬掩模，其中硬掩模包括形成在第一掩模层上的第一掩模层和第二掩模层。蚀刻衬底以形成沟槽。沟槽填充有场氧化物材料。使用第一蚀刻技术从存储器件剥离第二掩模层，并且使用第二蚀刻技术将第一掩模层从存储器件剥离，其中第二蚀刻技术不同于第一蚀刻技术。

8. 发明授权

US07572727B1 Semiconductor formation method that utilizes multiple etch stop layers 有权
标题翻译：利用多个蚀刻停止层的半导体形成方法
公开(公告)号：US07572727B1
公开(公告)日：2009-08-11
申请号：US10934828
申请日：2004-09-02
申请人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
发明人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76804 , H01L21/76829 , H01L21/76831 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.
摘要翻译：本发明是一种半导体接触形成系统和方法。接触绝缘区域形成有多个有助于形成接触的蚀刻停止子层。该接触形成工艺提供了相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。在一个实施例中，沉积包括多个蚀刻停止层的多次蚀刻停止绝缘层。通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除在金属层附近，并且更靠近基底的部分被去除。通过在多个蚀刻停止绝缘层中由多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现不同的接触区域宽度。导电材料（例如，钨）沉积在接触区域中。

9. 发明授权

US06969654B1 Flash NVROM devices with UV charge immunity 有权
标题翻译：具有UV电荷免疫功能的闪存NVROM器件
公开(公告)号：US06969654B1
公开(公告)日：2005-11-29
申请号：US09727714
申请日：2000-11-28
申请人： Tuan Duc Pham , Mark T. Ramsbey , Jeffrey A. Shields , Angela T. Hui , Dawn Hopper
发明人： Tuan Duc Pham , Mark T. Ramsbey , Jeffrey A. Shields , Angela T. Hui , Dawn Hopper
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L23/552 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/28273 , H01L23/552 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions so as to prevent electron mobility sufficient to render the cells unprogrammable or unerasable. The reduced electron migration during processing of the NVROM leads to increased yield and reliability of the devices.
摘要翻译：一种在制造期间防止闪存NVROM单元的紫外线充电的方法和由此形成的装置。在器件制造期间，在阻挡层上沉积UV阻挡层。 UV阻挡层基本上阻止UV进入栅极区域，以便防止电子迁移率足以使电池不可编程或不可擦除。在NVROM处理期间减少的电子迁移导致器件的产量和可靠性的提高。

10. 发明授权

US06808996B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06808996B1
公开(公告)日：2004-10-26
申请号：US09376659
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

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