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1. 发明授权

US07370263B1 Hardware efficient CRC generator for high speed communication networks 有权
标题翻译：用于高速通信网络的硬件高效CRC发生器
公开(公告)号：US07370263B1
公开(公告)日：2008-05-06
申请号：US11285761
申请日：2005-11-21
申请人： Andy P. Annadurai , Chris Tsu , Feng Han , Hong-Ming Li
发明人： Andy P. Annadurai , Chris Tsu , Feng Han , Hong-Ming Li
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6502
摘要： A cyclic redundancy check (CRC) generator, in accordance with a specific embodiment of the present invention, generates a 32-bit CRC for each packet whose data bytes are carried over a 128-bit bus by first dividing the data bytes by a 123nd degree generator polynomial and subsequently dividing the remainder of the first division by a 32nd degree generator polynomial. Data bytes of a new packet are divided by a different dividing logic than those of a current packet. The remainder of division performed on the bytes of a new packet are supplied to the dividing logic adapted to divide the bytes of a current packet. The division by the 123nd degree generator polynomial is performed on a per byte basis, with the remainder of the division of the (i+1)th byte being used in the division of the ith byte.
摘要翻译：根据本发明的具体实施例的循环冗余校验（CRC）生成器通过首先将数据字节除以123 < SUP> rd 度生成多项式，然后将第一除法的剩余部分除以32 度生成多项式。新分组的数据字节除了与当前分组的分割逻辑不同的分割逻辑。对新分组的字节执行的除法的剩余部分被提供给适于划分当前分组的字节的分割逻辑。按照每个字节执行123 ^{nd 度生成多项式的除法，其中在（i + 1）^{th字节的除法的余数划分第i个字节。}}

2. 再颁专利

USRE43218E1 Circuit and method for processing communication packets and valid data bytes 有权
标题翻译：用于处理通信包和有效数据字节的电路和方法
公开(公告)号：USRE43218E1
公开(公告)日：2012-02-28
申请号：US12215662
申请日：2008-06-27
申请人： Andy P. Annadurai , Feng Han , Mohammed Rahman , Chris Tsu
发明人： Andy P. Annadurai , Feng Han , Mohammed Rahman , Chris Tsu
IPC分类号： H04L12/56 , H04J1/16
CPC分类号： H04L69/08
摘要： Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.
摘要翻译：在诸如同步光网络（SONET）的通信系统内处理数据分组的方法和装置检测无效字节，并丢弃和移位数据字节以寻址无效字节。根据本发明的一个实施例的方法包括在通信系统中接收第一数据分组。此后，确定该分组是否以有效字节和数据的无效字节两者结束。如果有效字节和无效字节都存在，则无效字节被丢弃，并且来自后续数据包的有效字节与第一数据包的有效字节连接，字节移位发生在后续数据包中。字节移位继续，直到遇到无效字节结束的第二个数据包。在无效字节的第二个数据包结束时跳过一个时钟周期会导致只包含有效数据的数据包。

3. 发明授权

US07130317B2 Method and circuit for de-skewing data in a communication system 有权
公开(公告)号：US07130317B2
公开(公告)日：2006-10-31
申请号：US09988896
申请日：2001-11-19
申请人： Andy P. Annadurai , Feng Han , Mohammed Rahman , Chris Tsu
发明人： Andy P. Annadurai , Feng Han , Mohammed Rahman , Chris Tsu
IPC分类号： H04J3/06 , H04J3/00 , G06F1/12 , G06F15/16 , G06F13/42
CPC分类号： H04L1/242 , H04J3/047 , H04J3/0602 , H04J2203/0089 , H04L7/10
摘要： Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.

4. 发明授权

US07068673B2 Circuit and method for processing communication packets and valid data bytes 有权
公开(公告)号：US07068673B2
公开(公告)日：2006-06-27
申请号：US10087228
申请日：2002-02-27
申请人： Andy P. Annadurai , Feng Han , Mohammed Rahman , Chris Tsu
发明人： Andy P. Annadurai , Feng Han , Mohammed Rahman , Chris Tsu
IPC分类号： H04L12/56
CPC分类号： H04L69/08
摘要： Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.

5. 发明授权

US07643517B2 Method and circuit for de-skewing data in a communication system 失效
标题翻译：用于在通信系统中去偏转数据的方法和电路
公开(公告)号：US07643517B2
公开(公告)日：2010-01-05
申请号：US11514358
申请日：2006-08-30
申请人： Andy P. Annadurai , Feng Han , Mohammed Rahman , Chris Tsu
发明人： Andy P. Annadurai , Feng Han , Mohammed Rahman , Chris Tsu
IPC分类号： H04J3/06
CPC分类号： H04L1/242 , H04J3/047 , H04J3/0602 , H04J2203/0089 , H04L7/10
摘要： Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.
摘要翻译：用于在诸如SONET的数据通信网络中去偏斜数据的方法和电路。数据从系统芯片发送到数据失真的成帧器芯片。为了检测数据偏移，系统芯片向成帧器芯片发送训练序列。搜索发送到成帧器芯片的信息比特，以便检测训练序列。训练序列包含清除的转换模式，在该模式下，发送数据和TCTL信号线的所有16位都被反转。如果任何位没有反转，则该位必须是倾斜位。基于前一个时钟周期的数据和该转换之后的一个时钟周期，可以纠正偏移位。在检测到数据偏移之后，使用复用逻辑电路来在转换之前或之后基于一个时钟周期校正偏斜。复用逻辑电路包括耦合到多路复用逻辑电路的输入的至少三个寄存器。

6. 发明授权

US07318188B1 Hardware-efficient CRC generator for high speed communication networks 有权
标题翻译：用于高速通信网络的硬件高效CRC发生器
公开(公告)号：US07318188B1
公开(公告)日：2008-01-08
申请号：US11233920
申请日：2005-09-22
申请人： Andy P. Annadurai , Chris Tsu , Feng Han , Hon-Ming Li
发明人： Andy P. Annadurai , Chris Tsu , Feng Han , Hon-Ming Li
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6502
摘要： A cyclic redundancy check (CRC) generator, in accordance with a specific embodiment of the present invention, generates a 32-bit CRC for each packet whose data bytes are carried over a 128-bit bus by first dividing the data bytes by a 123nd degree generator polynomial and subsequently dividing the remainder of the first division by a 32nd degree generator polynomial. Data bytes of a new packet are divided by a different dividing logic than those of a current packet. The remainder of division performed on the bytes of a new packet are supplied to the dividing logic adapted to divide the bytes of a current packet. The division by the 123nd degree generator polynomial is performed on a per byte basis, with the remainder of the division of the (i+1)th byte being used in the division of the ith byte.
摘要翻译：根据本发明的具体实施例的循环冗余校验（CRC）生成器通过首先将数据字节除以123 < SUP> rd 度生成多项式，然后将第一除法的剩余部分除以32 度生成多项式。新分组的数据字节除了与当前分组的分割逻辑不同的分割逻辑。对新分组的字节执行的除法的剩余部分被提供给适于划分当前分组的字节的分割逻辑。按照每个字节执行123 ^{nd 度生成多项式的除法，其中在第（i + 1）个第字节的除法余数中划分第i个字节。}

7. 发明授权

US06968492B1 Hardware-efficient CRC generator for high speed communication networks 有权
标题翻译：用于高速通信网络的硬件高效CRC发生器
公开(公告)号：US06968492B1
公开(公告)日：2005-11-22
申请号：US10113469
申请日：2002-03-28
申请人： Andy P. Annadurai , Chris Tsu , Feng Han , Hon-Ming Li
发明人： Andy P. Annadurai , Chris Tsu , Feng Han , Hon-Ming Li
IPC分类号： H03M13/00 , H03M13/09
CPC分类号： H03M13/091 , H03M13/6502
摘要： A cyclic redundancy check (CRC) generator, in accordance with a specific embodiment of the present invention, generates a 32-bit CRC for each packet whose data bytes are carried over a 128-bit bus by first dividing the data bytes by a 123nd degree generator polynomial and subsequently dividing the remainder of the first division by a 32nd degree generator polynomial. Data bytes of a new packet are divided by a different dividing logic than those of a current packet. The remainder of division performed on the bytes of a new packet are supplied to the dividing logic adapted to divide the bytes of a current packet. The division by the 123nd degree generator polynomial is performed on a per byte basis, with the remainder of the division of the (i+1)th byte being used in the division of the ith byte.
摘要翻译：根据本发明的具体实施例的循环冗余校验（CRC）生成器通过首先将数据字节除以123 < SUP> nd 度生成多项式，然后将第一除法的剩余部分除以32 度生成多项式。新分组的数据字节除了与当前分组的分割逻辑不同的分割逻辑。对新分组的字节执行的除法的剩余部分被提供给适于划分当前分组的字节的分割逻辑。按照每个字节执行由123 ^{nd 度生成多项式的除法，其中在第（i + 1）个第字节的除法余数中划分第i个字节。}

8. 发明授权

US5811995A Circuit for switching between different frequency clock domains that are out of phase 失效
标题翻译：用于在不同频段的不同频率时钟域之间切换的电路
公开(公告)号：US5811995A
公开(公告)日：1998-09-22
申请号：US691832
申请日：1996-08-02
申请人： Rajat Roy , Jerry Kuo , Andy P. Annadurai
发明人： Rajat Roy , Jerry Kuo , Andy P. Annadurai
IPC分类号： G06F1/08 , H04L7/00 , H03K5/13 , H03K17/00
CPC分类号： H04L7/0083 , G06F1/08
摘要： A circuit and method for switching between different frequency clock domains that are out of phase. The circuit has a select input for selecting which frequency domain is to be output, a first circuit associated with the first clock domain, and a second circuit associated with the second clock domain. The first and second circuits are responsive to the select input and work together to disengage the first clock before the second clock is engaged.
摘要翻译：用于在不同频率的不同频率时钟域之间切换的电路和方法。电路具有用于选择要输出哪个频域的选择输入，与第一时钟域相关联的第一电路以及与第二时钟域相关联的第二电路。第一和第二电路响应于选择输入并一起工作以在第二时钟接合之前解除第一时钟。

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