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1. 发明授权

US08711614B1 Memory elements with increased write margin and soft error upset immunity 有权
标题翻译：存储器元件具有增加的写入裕度和软错误失真的抗扰度
公开(公告)号：US08711614B1
公开(公告)日：2014-04-29
申请号：US13052374
申请日：2011-03-21
申请人： Andy L. Lee , Irfan Rahim , Lu Zhou , Madhuri Mailavaram , Srinivas Perisetty
发明人： Andy L. Lee , Irfan Rahim , Lu Zhou , Madhuri Mailavaram , Srinivas Perisetty
IPC分类号： G11C11/34
CPC分类号： G11C8/10
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.
摘要翻译：提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。存储器元件可以各自具有形成双稳态元件和一对地址晶体管的四个反相器状晶体管对。晶体管中可能存在四个节点，每个节点与四个逆变器状晶体管对中的相应一个相关联。可以存在两个控制晶体管，每个控制晶体管耦合在逆变器状晶体管对的相应一个中的晶体管之间。在数据写入操作期间，可以关闭两个控制晶体管，以暂时将四个反相器状晶体管对中的两个中的晶体管去耦。

2. 发明授权

US07920410B1 Memory elements with increased write margin and soft error upset immunity 有权
标题翻译：存储器元件具有增加的写入裕度和软错误失真的抗扰度
公开(公告)号：US07920410B1
公开(公告)日：2011-04-05
申请号：US12391230
申请日：2009-02-23
申请人： Andy L. Lee , Irfan Rahim , Lu Zhou , Madhuri Mailavaram , Srinivas Perisetty
发明人： Andy L. Lee , Irfan Rahim , Lu Zhou , Madhuri Mailavaram , Srinivas Perisetty
IPC分类号： G11C11/00 , G11C5/06
CPC分类号： G11C8/10
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.
摘要翻译：提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。存储器元件可以各自具有形成双稳态元件和一对地址晶体管的四个反相器状晶体管对。晶体管中可能存在四个节点，每个节点与四个逆变器状晶体管对中的相应一个相关联。可以存在两个控制晶体管，每个控制晶体管耦合在逆变器状晶体管对的相应一个中的晶体管之间。在数据写入操作期间，可以关闭两个控制晶体管，以暂时将四个反相器状晶体管对中的两个中的晶体管去耦。

3. 发明授权

US08081502B1 Memory elements with body bias control 有权
标题翻译：记忆元素与身体偏差控制
公开(公告)号：US08081502B1
公开(公告)日：2011-12-20
申请号：US12345560
申请日：2008-12-29
申请人： Irfan Rahim , Jun Liu , Andy L. Lee , William Bradley Vest , Lu Zhou , Qi Xiang , Yanzhong Yu , Jeffrey Xiaoqi Tung , Albert Ratnakumar
发明人： Irfan Rahim , Jun Liu , Andy L. Lee , William Bradley Vest , Lu Zhou , Qi Xiang , Yanzhong Yu , Jeffrey Xiaoqi Tung , Albert Ratnakumar
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.
摘要翻译：提供了一种具有存储元件的集成电路。存储器元件可以具有带有主体端子的存储器元件晶体管。体偏置控制电路可以提供加强或削弱存储元件晶体管的体偏置电压，以改善读和写余量。体偏置控制电路可以动态地控制体偏置电压，从而将时变体偏置电压提供给存储元件晶体管。存储元件中的地址晶体管和锁存晶体管可以被选择性地加强和削弱。过程变化可以通过削弱快速晶体管和加强具有体偏置调整的慢晶体管来补偿。

4. 发明申请

US20120039142A1 SCALEABLE LOOK-UP TABLE BASED MEMORY 有权
标题翻译：可扩展的基于表的记忆
公开(公告)号：US20120039142A1
公开(公告)日：2012-02-16
申请号：US13277871
申请日：2011-10-20
申请人： Philip Pan , Andy L. Lee , Lu Zhou , Aniket Kadkol
发明人： Philip Pan , Andy L. Lee , Lu Zhou , Aniket Kadkol
IPC分类号： G11C7/12 , G11C5/14
CPC分类号： G11C11/418 , G11C7/00 , G11C7/1045 , G11C7/1048 , G11C7/12 , G11C7/22 , G11C8/10 , G11C11/4094 , G11C11/413 , G11C11/419 , G11C29/12 , G11C2029/0409 , G11C2029/1204 , G11C2029/2602
摘要： An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.
摘要翻译：提供一种集成电路，其具有包括可转换地用作配置随机存取存储器（CRAM）或静态随机存取存储器（SRAM））的存储元件阵列的逻辑元件。逻辑元件包括具有专用复用器的第一和第二对数据路径。在一个实施例中，第一和第二对数据路径被复用到阵列行的位线。逻辑元件还包括数据路径控制块，其产生用于每个专用多路复用器的控制信号。控制信号确定存储元件是否用作CRAM或SRAM。提供了一种用于在CRAM模式和SRAM模式之间选择性地配置存储器阵列的方法。

5. 发明授权

US07948792B1 Memory and techniques for using same 有权
标题翻译：内存和技术使用相同
公开(公告)号：US07948792B1
公开(公告)日：2011-05-24
申请号：US12424362
申请日：2009-04-15
申请人： Andy L. Lee , Lu Zhou
发明人： Andy L. Lee , Lu Zhou
IPC分类号： G11C11/00 , G11C7/10 , G06F7/38
CPC分类号： G11C11/413 , G11C8/08
摘要： There are provided methods and devices for providing overdrive voltages to address lines to help prevent leakage current in semiconductor memories, such as configuration memories used with programmable logic devices. Specifically, for example, there is provided a memory that includes an array of memory cells. Each memory cell includes a retainer circuit. An access transistor is coupled to the retainer circuit. An overdrive voltage level may be applied to the access transistor.
摘要翻译：提供了用于向地址线提供过驱动电压以帮助防止半导体存储器（例如与可编程逻辑器件一起使用的配置存储器）中的漏电流的方法和装置。具体地，例如，提供了包括存储器单元阵列的存储器。每个存储单元包括保持器电路。存取晶体管耦合到保持器电路。可以将过驱动电压电平施加到存取晶体管。

6. 发明授权

US08064280B1 Scaleable look-up table based memory 有权
标题翻译：基于可扩展查询表的内存
公开(公告)号：US08064280B1
公开(公告)日：2011-11-22
申请号：US12136201
申请日：2008-06-10
申请人： Philip Pan , Andy L. Lee , Lu Zhou , Aniket Kadkol
发明人： Philip Pan , Andy L. Lee , Lu Zhou , Aniket Kadkol
IPC分类号： G11C5/14
CPC分类号： G11C11/418 , G11C7/00 , G11C7/1045 , G11C7/1048 , G11C7/12 , G11C7/22 , G11C8/10 , G11C11/4094 , G11C11/413 , G11C11/419 , G11C29/12 , G11C2029/0409 , G11C2029/1204 , G11C2029/2602
摘要： An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.
摘要翻译：提供一种集成电路，其具有包括可转换地用作配置随机存取存储器（CRAM）或静态随机存取存储器（SRAM））的存储元件阵列的逻辑元件。逻辑元件包括具有专用复用器的第一和第二对数据路径。在一个实施例中，第一和第二对数据路径被复用到阵列行的位线。逻辑元件还包括数据路径控制块，其产生用于每个专用多路复用器的控制信号。控制信号确定存储元件是否用作CRAM或SRAM。提供了一种用于在CRAM模式和SRAM模式之间选择性地配置存储器阵列的方法。

7. 发明授权

US08644100B2 Scaleable look-up table based memory 有权
标题翻译：基于可扩展查询表的内存
公开(公告)号：US08644100B2
公开(公告)日：2014-02-04
申请号：US13277871
申请日：2011-10-20
申请人： Philip Pan , Andy L. Lee , Lu Zhou , Aniket Kadkol
发明人： Philip Pan , Andy L. Lee , Lu Zhou , Aniket Kadkol
IPC分类号： G11C7/00
CPC分类号： G11C11/418 , G11C7/00 , G11C7/1045 , G11C7/1048 , G11C7/12 , G11C7/22 , G11C8/10 , G11C11/4094 , G11C11/413 , G11C11/419 , G11C29/12 , G11C2029/0409 , G11C2029/1204 , G11C2029/2602
摘要： An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.
摘要翻译：提供一种集成电路，其具有包括可转换地用作配置随机存取存储器（CRAM）或静态随机存取存储器（SRAM））的存储元件阵列的逻辑元件。逻辑元件包括具有专用复用器的第一和第二对数据路径。在一个实施例中，第一和第二对数据路径被复用到阵列行的位线。逻辑元件还包括数据路径控制块，其产生用于每个专用多路复用器的控制信号。控制信号确定存储元件是否用作CRAM或SRAM。提供了一种用于在CRAM模式和SRAM模式之间选择性地配置存储器阵列的方法。

8. 发明授权

US08436646B1 Reconfigurable logic block with user RAM 有权
标题翻译：用户RAM可重构逻辑块
公开(公告)号：US08436646B1
公开(公告)日：2013-05-07
申请号：US13175662
申请日：2011-07-01
申请人： David W. Mendel , Triet M. Nguyen , Lu Zhou , Gary Lai
发明人： David W. Mendel , Triet M. Nguyen , Lu Zhou , Gary Lai
IPC分类号： H03K19/173
CPC分类号： H03K19/17724
摘要： A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. If the mode flag indicates a design state, the configuration logic associated with the logic block is included in data verification and correction processes. If the mode flag indicates a user defined state, the configuration logic associated with the logic block is excluded from data verification and correction processes. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state without causing deleterious effects.
摘要翻译：可编程逻辑器件包括诸如可被配置为随机存取存储器（RAM）或查找表（LUT）的逻辑阵列块（LAB）的逻辑块。提供模式标志以指示诸如在逻辑块的部分重新配置期间使用的配置RAM（CRAM）的配置逻辑的操作模式。如果模式标志指示设计状态，则与逻辑块相关联的配置逻辑被包括在数据验证和校正处理中。如果模式标志指示用户定义的状态，则与逻辑块相关联的配置逻辑从数据验证和校正处理中排除。因此，排除和包含来自数据验证和校正处理的配置逻辑区域的部分允许配置逻辑的区域既存储设计状态又限制用户定义的状态，而不会造成有害影响。

9. 发明授权

US08572538B2 Reconfigurable logic block 有权
公开(公告)号：US08572538B2
公开(公告)日：2013-10-29
申请号：US13369226
申请日：2012-02-08
申请人： David W. Mendel , Gary Lai , Lu Zhou , Bruce B. Pedersen
发明人： David W. Mendel , Gary Lai , Lu Zhou , Bruce B. Pedersen
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F17/5054 , G06F11/1008 , H03K19/17756 , H03K19/17776
摘要： A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

10. 发明授权

US08242806B1 Methods and systems for managing a write operation 有权
标题翻译：用于管理写入操作的方法和系统
公开(公告)号：US08242806B1
公开(公告)日：2012-08-14
申请号：US12829206
申请日：2010-07-01
申请人： David Cashman , David Lewis , Lu Zhou
发明人： David Cashman , David Lewis , Lu Zhou
IPC分类号： G06F7/38
CPC分类号： H03K19/17728
摘要： Systems and methods for managing a write operation are described. The systems include a logic element (LE) including an N-input look-up table (LUT) having a configurable random access memory (CRAM) including 2N memory cells. The systems further include a write address decoder coupled to the LE and a write address hard logic register that stores an address of one of the memory cells. N is an integer. The hard logic register removes a dependency of a timing relationship between a write address launch and a write to the CRAM on a design of an integrated circuit.
摘要翻译：描述用于管理写入操作的系统和方法。该系统包括包括具有包括2N个存储单元的可配置随机存取存储器（CRAM））的N输入查找表（LUT）的逻辑元件（LE）。系统还包括耦合到LE的写地址解码器和存储存储器单元之一的地址的写地址硬逻辑寄存器。 N是整数。硬逻辑寄存器消除了对集成电路设计的写入地址启动和对CRAM的写入之间的定时关系的依赖性。

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