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1. 发明申请

US20140181464A1 COALESCING ADJACENT GATHER/SCATTER OPERATIONS 有权
标题翻译：加油相机/散热器操作
公开(公告)号：US20140181464A1
公开(公告)日：2014-06-26
申请号：US13997784
申请日：2012-12-26
申请人： Andrew T. Forsyth , Brian J. Hickmann , Jonathan C. Hall , Christopher J. Hughes
发明人： Andrew T. Forsyth , Brian J. Hickmann , Jonathan C. Hall , Christopher J. Hughes
IPC分类号： G06F12/10
CPC分类号： G06F9/3853 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30098 , G06F9/30105 , G06F9/30145 , G06F9/3804 , G06F9/3824 , G06F9/3836 , G06F9/3887 , G06F12/0875 , G06F12/1027 , G06F13/4282 , G06F15/8007 , G06F2212/1016 , G06F2212/452 , G06F2212/68
摘要： According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于解码从存储器收集数据元素的第一指令，所述第一指令具有指定第一存储位置的第一操作数和指定存储多个数据元素的第一存储器地址的第二操作数。处理器还包括执行单元，其响应于第一指令而耦合到指令解码器，基于由第二操作数指示的第一存储器地址从存储器位置读取连续的第一和第二数据元素，并且将所述第一数据元素存储在所述第一存储位置的第一条目中，以及将第二数据元素存储在与所述第一存储位置的所述第一条目相对应的第二存储位置的第二条目中。

2. 发明申请

US20120166761A1 VECTOR CONFLICT INSTRUCTIONS 有权
标题翻译：矢量冲突指示
公开(公告)号：US20120166761A1
公开(公告)日：2012-06-28
申请号：US12976616
申请日：2010-12-22
申请人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
发明人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30043 , G06F9/3838
摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
摘要翻译：描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

3. 发明授权

US08972698B2 Vector conflict instructions 有权
标题翻译：向量冲突指令
公开(公告)号：US08972698B2
公开(公告)日：2015-03-03
申请号：US12976616
申请日：2010-12-22
申请人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
发明人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30043 , G06F9/3838
摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
摘要翻译：描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

4. 发明申请

US20160041827A1 INSTRUCTIONS FOR MERGING MASK PATTERNS 审中-公开
标题翻译：用于合并掩蔽图案的说明
公开(公告)号：US20160041827A1
公开(公告)日：2016-02-11
申请号：US13995944
申请日：2011-12-23
申请人： Jesus Corbal , Matthew J Craighead , Dennis R Bradford , Jonathan C. Hall , Andrew T. Forsyth
发明人： Jesus Corbal , Matthew J Craighead , Dennis R Bradford , Jonathan C. Hall , Andrew T. Forsyth
IPC分类号： G06F9/30
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method is described that includes fetching an instruction and decoding the instruction. The method further includes fetching a first mask vector from a first mask register space location identified by the instruction. The method further includes fetching a second mask vector from a second mask register space location identified by the instruction. The method also includes executing the instruction by merging the first and second mask vectors into a single data structure and causing the single data structure to be written into a memory location identified by the instruction.
摘要翻译：描述了一种包括获取指令并解码指令的方法。该方法还包括从由该指令识别的第一屏蔽寄存器空间位置获取第一屏蔽矢量。该方法还包括从由该指令识别的第二屏蔽寄存器空间位置获取第二屏蔽矢量。该方法还包括通过将第一和第二屏蔽矢量合并为单个数据结构并使单个数据结构被写入由该指令识别的存储器位置来执行该指令。

5. 发明申请

US20120144089A1 SCATTER/GATHER ACCESSING MULTIPLE CACHE LINES IN A SINGLE CACHE PORT 审中-公开
标题翻译：散热器/ GATHER在单个缓存端口中访问多条缓存线
公开(公告)号：US20120144089A1
公开(公告)日：2012-06-07
申请号：US13250223
申请日：2011-09-30
申请人： Jonathan C. Hall , Sailesh Kottapalli , Andrew T. Forsyth
发明人： Jonathan C. Hall , Sailesh Kottapalli , Andrew T. Forsyth
IPC分类号： G06F12/08
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30036 , G06F9/30101 , G06F9/345 , G06F12/06 , G06F12/08
摘要： Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.
摘要翻译：公开了用于访问用于散射/收集操作的多条数据高速缓存行的方法和装置。设备的实施例可以包括地址生成逻辑，用于从具有第一值的一组对应的掩码元素中的每一个的索引集合的索引生成地址。线或库匹配排序逻辑匹配相同高速缓存行或不同库中的地址，并且订购访问序列以允许多个高速缓存行和不同存储体中的一组地址。地址选择逻辑将地址组指向高速缓存中的对应的不同存储体，以访问与单个访问周期中的地址组对应的多个高速缓存行中的数据元素。拆卸/重组缓冲器根据其各自的存储体/寄存器位置对数据元素进行排序，并且收集/散布有限状态机将相应的掩模元素的值从第一值改变为第二值。

6. 发明申请

US20140095779A1 PROCESSING MEMORY ACCESS INSTRUCTIONS THAT HAVE DUPLICATE MEMORY INDICES 有权
标题翻译：处理存储器访问指令，具有重复的存储器指示
公开(公告)号：US20140095779A1
公开(公告)日：2014-04-03
申请号：US13631378
申请日：2012-09-28
申请人： Andrew T. Forsyth , Dennis R. Bradford , Jonathan C. Hall
发明人： Andrew T. Forsyth , Dennis R. Bradford , Jonathan C. Hall
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/00 , G06F3/06 , G06F3/0608 , G06F3/0641 , G06F9/30 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F11/1453 , G06F12/0246
摘要： A method of an aspect includes receiving an instruction indicating a first source packed memory indices, a second source packed data operation mask, and a destination storage location. Memory indices of the packed memory indices are compared with one another. One or more sets of duplicate memory indices are identified. Data corresponding to each set of duplicate memory indices is loaded only once. The loaded data corresponding to each set of duplicate memory indices is replicated for each of the duplicate memory indices in the set. A packed data result in the destination storage location in response to the instruction. The packed data result includes data elements from memory locations that are indicated by corresponding memory indices of the packed memory indices when not blocked by corresponding elements of the packed data operation mask.
摘要翻译：一方面的方法包括接收指示第一源打包存储器索引的指令，第二源打包数据操作掩码和目的地存储位置。将打包的内存索引的内存索引彼此进行比较。识别一组或多组重复的内存索引。与每组重复存储器索引对应的数据仅加载一次。对于集合中的每个重复存储器索引，复制对应于每组重复存储器索引的加载数据。打包数据导致响应于该指令的目的地存储位置。打包数据结果包括来自存储器位置的数据元素，当不被打包数据操作掩码的相应元素阻塞时，由打包的存储器索引的相应存储器索引指示。

7. 发明授权

US10387151B2 Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks 有权
公开(公告)号：US10387151B2
公开(公告)日：2019-08-20
申请号：US13250223
申请日：2011-09-30
申请人： Jonathan C. Hall , Sailesh Kottapalli , Andrew T. Forsyth
发明人： Jonathan C. Hall , Sailesh Kottapalli , Andrew T. Forsyth
IPC分类号： G06F9/312 , G06F9/30 , G06F12/06 , G06F12/08 , G06F9/345
摘要： Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

8. 发明授权

US09766886B2 Instruction and logic to provide vector linear interpolation functionality 有权
公开(公告)号：US09766886B2
公开(公告)日：2017-09-19
申请号：US13977736
申请日：2011-12-16
申请人： Jesus Corbal , Andrew T. Forsyth , Lisa K. Wu , Thomas D. Fletcher
发明人： Jesus Corbal , Andrew T. Forsyth , Lisa K. Wu , Thomas D. Fletcher
IPC分类号： G06F9/302 , G06F9/315 , G06F17/17 , G09G5/00 , G06F15/76 , G06F9/30 , G06F9/38 , G06T3/40 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30007 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30109 , G06F9/30145 , G06F9/3016 , G06F9/30185 , G06F9/3836 , G06F15/8053 , G06F17/17 , G06T3/4007
摘要： Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.

9. 发明授权

US09733935B2 Super multiply add (super madd) instruction 有权
公开(公告)号：US09733935B2
公开(公告)日：2017-08-15
申请号：US13976404
申请日：2011-12-23
申请人： Jesus Corbal , Andrew T. Forsyth , Roger Espasa , Manel Fernandez , Thomas D. Fletcher
发明人： Jesus Corbal , Andrew T. Forsyth , Roger Espasa , Manel Fernandez , Thomas D. Fletcher
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30101 , G06F9/30145
摘要： A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.

10. 发明申请

US20110148894A1 DEMAND-PAGED TEXTURES 有权
标题翻译：需要的纹理
公开(公告)号：US20110148894A1
公开(公告)日：2011-06-23
申请号：US12642917
申请日：2009-12-21
申请人： Jean-Luc Duprat , Paul Lalonde , Andrew T. Forsyth
发明人： Jean-Luc Duprat , Paul Lalonde , Andrew T. Forsyth
IPC分类号： G06T11/40
CPC分类号： G06T11/001 , G06T9/00 , G06T15/04 , H04N19/60
摘要： A method and system may include a chip having graphics rendering hardware, a cache and a processor to execute an application with texture allocation logic to receive notification of a page miss from the graphics rendering hardware. The logic can map the page miss to a tile of a texture image, store the tile as an entry to the cache, and map the entry to a virtual address space of a virtual image corresponding to the texture image. The system may also include off-chip memory to store the texture image.
摘要翻译：方法和系统可以包括具有图形绘制硬件的芯片，高速缓存和处理器，以执行具有纹理分配逻辑的应用，以从图形呈现硬件接收页面未命中的通知。逻辑可以将页面未命中映射到纹理图像的瓦片，将瓦片作为条目存储到高速缓存，并将条目映射到与纹理图像相对应的虚拟图像的虚拟地址空间。该系统还可以包括用于存储纹理图像的片外存储器。

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