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2. 发明申请

US20070105731A1 Lubricating oil compositions 审中-公开
标题翻译：润滑油组成
公开(公告)号：US20070105731A1
公开(公告)日：2007-05-10
申请号：US11266789
申请日：2005-11-04
申请人： Chin Chu , Rolfe Hartley , Stuart Briggs , Jacob Emert , Jai Bansal
发明人： Chin Chu , Rolfe Hartley , Stuart Briggs , Jacob Emert , Jai Bansal
IPC分类号： C10L1/22
CPC分类号： C10M143/00 , C10M161/00 , C10M169/041 , C10M2203/1006 , C10M2205/022 , C10M2205/026 , C10M2205/028 , C10M2205/04 , C10M2205/08 , C10M2207/14 , C10M2207/262 , C10M2215/28 , C10M2223/045 , C10M2229/02 , C10N2220/021 , C10N2220/033 , C10N2230/02 , C10N2230/40 , C10N2230/42 , C10N2230/43 , C10N2230/45 , C10N2230/68 , C10N2240/10 , C10N2240/102 , C10N2240/103 , C10M2205/024 , C10M2205/06 , C10N2260/02 , C10N2210/02
摘要： A lubricating oil composition formulated with a viscosity index (VI) improver composition including a combination of an ethylene α-olefin copolymer having no greater than 66 mass % of units derived from ethylene, and a linear diblock copolymer including at least one block derived primarily from a vinyl aromatic hydrocarbon monomer, and at least one block derived primarily from diene monomer.
摘要翻译：用粘度指数（VI）改进剂组合物配制的润滑油组合物，其包含不大于66质量％的衍生自乙烯的单元的乙烯α-烯烃共聚物和包含至少一个主要来自乙烯基芳族烃单体和至少一种主要来自二烯单体的嵌段。

3. 发明申请

US20050275432A1 High voltage tolerant off chip driver circuit 有权
标题翻译：高耐压片外驱动电路
公开(公告)号：US20050275432A1
公开(公告)日：2005-12-15
申请号：US11107607
申请日：2005-04-15
申请人： Jai Bansal
发明人： Jai Bansal
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315
摘要： An off chip driver circuit includes a pre-driver circuit and a driver circuit. Driver data and enable inputs are decoded in the pre-driver circuit to provide independent inputs to pull up and pull down transistors in the driver circuit. The enable input keeps the driver circuit in the active or high impedance modes. A feedback signal generated by the driver output and the driver enable signals controls an inverter circuit within the driver circuit to provide proper biasing conditions at the gate of the pull up transistor. This feed back provides fast switching times for the driver circuit and prevents gate oxide of all the transistors from being overstressed by the external high voltage signal.
摘要翻译：片外驱动电路包括预驱动电路和驱动电路。驱动器数据和使能输入在预驱动器电路中被解码，以提供独立的输入以在驱动器电路中上拉和下拉晶体管。使能输入保持驱动电路处于有效或高阻抗模式。由驱动器输出和驱动器使能信号产生的反馈信号控制驱动器电路内的反相器电路，以在上拉晶体管的栅极处提供适当的偏置条件。该反馈提供了驱动电路的快速切换时间，并且防止所有晶体管的栅极氧化物被外部高电压信号过载。

4. 发明申请

US20060015828A1 Method for designing structured ASICS in silicon processes with three unique masking steps 有权
标题翻译：在具有三个独特掩蔽步骤的硅工艺中设计结构化ASICS的方法
公开(公告)号：US20060015828A1
公开(公告)日：2006-01-19
申请号：US11147024
申请日：2005-06-07
申请人： Jai Bansal
发明人： Jai Bansal
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.
摘要翻译：多功能核心基站包括一组功能微电路。这些微电路用于设计逻辑函数库。由一个或多个微电路组成的功能宏具有类似于常规标准单元库宏集的固定和完整的物理布局。除了核心功能宏集之外，库中还定义了主输入/输出缓冲区和常用的单端口和双端口存储器块。该库包括所有的ASIC综合，仿真和物理设计规则。

5. 发明申请

US20050034095A1 Method for providing a cell-based ASIC device with multiple power supply voltages 有权
标题翻译：为基于单元的ASIC设备提供多个电源电压的方法
公开(公告)号：US20050034095A1
公开(公告)日：2005-02-10
申请号：US10634229
申请日：2003-08-05
申请人： Jai Bansal
发明人： Jai Bansal
IPC分类号： G06F17/50 , H02J1/08
CPC分类号： G06F17/5068 , H02J1/08 , H02J2001/008
摘要： A method for designing a cell-based ASIC device with multiple power supply voltages is disclosed. An ASIC chip image is made without applying power or ground buses to metal layer M1. All fast or high-power circuits are grouped together into high-power logic blocks and synthesized with high-power circuit macro libraries. All slow or low-power circuits are grouped together into low-power logic blocks and synthesized with low power circuit macro libraries. The associate power and ground buses are applied to metal layer M1 in each of the logic blocks. The logic blocks are placed on the ASIC so that different voltage groups are separated by at least one cell. The ASIC is then routed and tested before the mask is released.
摘要翻译：公开了一种用于设计具有多个电源电压的基于单元的ASIC器件的方法。在不向金属层M1施加电力或接地总线的情况下制造ASIC芯片图像。所有快速或高功率电路都分组成大功率逻辑块，并与大功率电路宏库合成。所有慢速或低功耗电路都分组成低功耗逻辑块，并与低功耗电路宏库合成。相应的电源和接地总线被施加到每个逻辑块中的金属层M1。逻辑块被放置在ASIC上，使得不同的电压组被至少一个单元隔开。然后在掩模释放之前，将ASIC路由和测试。

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