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1. 发明授权

US07056773B2 Backgated FinFET having different oxide thicknesses 失效
公开(公告)号：US07056773B2
公开(公告)日：2006-06-06
申请号：US10709323
申请日：2004-04-28
申请人： Andres Bryant , Omer H. Dokumaci , Hussein I. Hanafi , Edward J. Nowak
发明人： Andres Bryant , Omer H. Dokumaci , Hussein I. Hanafi , Edward J. Nowak
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L29/785 , H01L29/42368 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.

2. 发明授权

US07187042B2 Backgated FinFET having different oxide thicknesses 失效
标题翻译：背衬FinFET具有不同的氧化物厚度
公开(公告)号：US07187042B2
公开(公告)日：2007-03-06
申请号：US11365504
申请日：2006-03-02
申请人： Andres Bryant , Omer H. Dokumaci , Hussein I. Hanafi , Edward J. Nowak
发明人： Andres Bryant , Omer H. Dokumaci , Hussein I. Hanafi , Edward J. Nowak
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/42368 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.
摘要翻译：在前栅侧和后栅极侧制造具有不同介电层厚度的背景FinFET的方法包括将杂质引入FinFET的鳍的至少一侧的步骤，以形成不同厚度的电介质层。可以通过注入引入的杂质增强或延迟电介质形成。

3. 发明授权

US07476946B2 Backgated FinFET having different oxide thicknesses 有权
标题翻译：背衬FinFET具有不同的氧化物厚度
公开(公告)号：US07476946B2
公开(公告)日：2009-01-13
申请号：US11427222
申请日：2006-06-28
申请人： Andres Bryant , Omer H. Dokumaci , Hussein I Hanafi , Edward J. Nowak
发明人： Andres Bryant , Omer H. Dokumaci , Hussein I Hanafi , Edward J. Nowak
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/42368 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.
摘要翻译：在前栅侧和后栅极侧制造具有不同介电层厚度的背景FinFET的方法包括将杂质引入FinFET的鳍的至少一侧的步骤，以形成不同厚度的电介质层。可以通过注入引入的杂质增强或延迟电介质形成。

4. 发明申请

US20090261425A1 FINFETs SINGLE-SIDED IMPLANT FORMATION 有权
标题翻译： FINFET单面植入物形成
公开(公告)号：US20090261425A1
公开(公告)日：2009-10-22
申请号：US12106476
申请日：2008-04-21
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Omer H. Dokumaci , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Omer H. Dokumaci , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336 , H01L21/84
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/66803 , H01L29/785
摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.
摘要翻译：一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。

5. 发明授权

US07994612B2 FinFETs single-sided implant formation 有权
标题翻译： FinFET单面植入物形成
公开(公告)号：US07994612B2
公开(公告)日：2011-08-09
申请号：US12106476
申请日：2008-04-21
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Omer H. Dokumaci , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Omer H. Dokumaci , Edward J. Nowak
IPC分类号： H01L21/02
CPC分类号： H01L21/26513 , H01L21/26586 , H01L29/66803 , H01L29/785
摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.
摘要翻译：一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。

6. 发明授权

US07732286B2 Buried biasing wells in FETs (Field Effect Transistors) 有权
标题翻译： FET中的埋置偏置阱（场效应晶体管）
公开(公告)号：US07732286B2
公开(公告)日：2010-06-08
申请号：US11845244
申请日：2007-08-27
申请人： Hussein I. Hanafi , Edward J. Nowak
发明人： Hussein I. Hanafi , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/105 , H01L29/0653 , H01L29/66628 , H01L29/7834
摘要： A method for fabricating a semiconductor structure. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.
摘要翻译：一种半导体结构的制造方法。半导体结构包括第一和第二源极/漏极区域; 设置在所述第一和第二源极/漏极区之间的沟道区; 与通道区域物理接触的掩埋阱区域; 并且埋置的阻挡区域设置在所述掩埋阱区域和所述第一源极/漏极区域之间并且设置在所述掩埋阱区域和所述第二源极/漏极区域之间，其中所述掩埋势垒区域适于防止所述掩埋阻挡区域之间的电流泄漏和掺杂剂扩散埋入阱区域和第一源极/漏极区域以及掩埋阱区域和第二源极/漏极区域之间。

7. 发明授权

US07271453B2 Buried biasing wells in FETS 失效
标题翻译： FET中埋置偏置井
公开(公告)号：US07271453B2
公开(公告)日：2007-09-18
申请号：US10711450
申请日：2004-09-20
申请人： Hussein I. Hanafi , Edward J. Nowak
发明人： Hussein I. Hanafi , Edward J. Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/105 , H01L29/0653 , H01L29/66628 , H01L29/7834
摘要： A structure of a semiconductor device and method for fabricating the same is disclosed. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.
摘要翻译：公开了半导体器件的结构及其制造方法。半导体结构包括第一和第二源极/漏极区域; 设置在所述第一和第二源极/漏极区之间的沟道区; 与通道区域物理接触的掩埋阱区域; 并且埋置的阻挡区域设置在所述掩埋阱区域和所述第一源极/漏极区域之间并且设置在所述掩埋阱区域和所述第二源极/漏极区域之间，其中所述掩埋势垒区域适于防止所述掩埋阻挡区域之间的电流泄漏和掺杂剂扩散埋入阱区域和第一源极/漏极区域以及掩埋阱区域和第二源极/漏极区域之间。

8. 发明授权

US09368410B2 Semiconductor devices having tensile and/or compressive stress and methods of manufacturing 有权
标题翻译：具有拉伸和/或压缩应力的半导体器件和制造方法
公开(公告)号：US09368410B2
公开(公告)日：2016-06-14
申请号：US12033280
申请日：2008-02-19
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Edmund J. Sprogis
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Edmund J. Sprogis
IPC分类号： H01L29/78 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76205 , H01L21/823878 , H01L29/7846
摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
摘要翻译：公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。第一氧化沟槽在通道中产生应变分量以增加器件性能。

9. 发明授权

US08617412B2 Nano-filter and method of forming same, and method of filtration 失效
标题翻译：纳米过滤器及其形成方法及过滤方法
公开(公告)号：US08617412B2
公开(公告)日：2013-12-31
申请号：US12966370
申请日：2010-12-13
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
IPC分类号： C23F3/00 , B01D29/46 , H01L21/02
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译：本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。纳米线结构可以包括多个垂直堆叠的水平纳米线。

10. 发明申请

US20130240997A1 CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD 审中-公开
标题翻译：用于修改半导体器件中的应力的接触棒及相关方法
公开(公告)号：US20130240997A1
公开(公告)日：2013-09-19
申请号：US13424319
申请日：2012-03-19
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L27/11 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823871 , H01L27/1104 , H01L29/7843
摘要： Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the stress inducing layer inducing only one of a compressive stress and a tensile stress; a contact bar extending through the stress inducing layer and coupled to at least one of the source/drain regions of a selected device of the PFET and the NFET to modify a stress induced in the selected device compared to a stress induced in the other device; and a round contact extending through the stress inducing layer and coupled to at least one of the source/drain regions of the other device of the PFET and the NFET.
摘要翻译：公开了用于形成应力优化接触棒和触点的解决方案。一方面，公开了一种具有源极/漏极区域的n型场效应晶体管（NFET）的半导体器件; 具有源极/漏极区域的p型场效应晶体管（PFET）在NFET和PFET两者上的应力诱导层，应力诱导层仅引起压缩应力和拉伸应力之一; 接触棒延伸穿过应力感应层并且耦合到PFET和NFET的所选器件的源/漏区中的至少一个，以修改与在另一器件中感应的应力相比在所选器件中感应的应力; 以及延伸穿过应力感应层并且耦合到PFET和NFET的另一个器件的源极/漏极区域中的至少一个的圆形接触。

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