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1. 发明申请

US20090067351A1 Power Detector Radio Frequency Multiplexer 审中-公开
公开(公告)号：US20090067351A1
公开(公告)日：2009-03-12
申请号：US11851398
申请日：2007-09-07
申请人： Andreas Wiesbauer , Sven Derksen , Stefano Marsili , Koen Mertens , Marc Tiebout
发明人： Andreas Wiesbauer , Sven Derksen , Stefano Marsili , Koen Mertens , Marc Tiebout
IPC分类号： H04B7/00
CPC分类号： H04W52/52 , H04B17/13
摘要： Implementations related to systems and devices that make use of a power detector multiplexer are presented herein.

2. 发明授权

US07643802B2 Mixer circuit and method for reducing an up-conversion mixer leakage 有权
标题翻译：混频器电路和减少上变频混频器泄漏的方法
公开(公告)号：US07643802B2
公开(公告)日：2010-01-05
申请号：US11492466
申请日：2006-07-25
申请人： Stefano Marsili , Andreas Wiesbauer , Marc Tiebout
发明人： Stefano Marsili , Andreas Wiesbauer , Marc Tiebout
IPC分类号： H04B1/04
CPC分类号： H04B1/525
摘要： A mixer circuit includes a first oscillator, a second oscillator, an up-conversion mixer, a down-conversion mixer, and a detect and control unit. The up-conversion mixer has a first input terminal coupled to the first oscillator and an output terminal. The down-conversion mixer has a first input terminal coupled to the output terminal of the up-conversion mixer and a second input terminal coupled to the second oscillator. The detect and control unit is coupled to the down-conversion mixer.
摘要翻译：混频器电路包括第一振荡器，第二振荡器，上变频混频器，下变频混频器以及检测和控制单元。上变换混频器具有耦合到第一振荡器的第一输入端和输出端。下转换混频器具有耦合到上转换混频器的输出端的第一输入端和耦合到第二振荡器的第二输入端。检测和控制单元耦合到下变频混频器。

3. 发明申请

US20080026708A1 Mixer circuit and method for reducing an up-conversion mixer leakage 有权
标题翻译：混频器电路和减少上变频混频器泄漏的方法
公开(公告)号：US20080026708A1
公开(公告)日：2008-01-31
申请号：US11492466
申请日：2006-07-25
申请人： Stefano Marsili , Andreas Wiesbauer , Marc Tiebout
发明人： Stefano Marsili , Andreas Wiesbauer , Marc Tiebout
IPC分类号： H04B1/04 , H01Q11/12
CPC分类号： H04B1/525
摘要： A mixer circuit includes a first oscillator, a second oscillator, an up-conversion mixer, a down-conversion mixer, and a detect and control unit. The up-conversion mixer has a first input terminal coupled to the first oscillator and an output terminal. The down-conversion mixer has a first input terminal coupled to the output terminal of the up-conversion mixer and a second input terminal coupled to the second oscillator. The detect and control unit is coupled to the down-conversion mixer.
摘要翻译：混频器电路包括第一振荡器，第二振荡器，上变频混频器，下变频混频器以及检测和控制单元。上变换混频器具有耦合到第一振荡器的第一输入端和输出端。下转换混频器具有耦合到上转换混频器的输出端的第一输入端和耦合到第二振荡器的第二输入端。检测和控制单元耦合到下变频混频器。

4. 发明授权

US07940830B2 Fast hopping frequency synthesizer 有权
标题翻译：快跳频率合成器
公开(公告)号：US07940830B2
公开(公告)日：2011-05-10
申请号：US11863037
申请日：2007-09-27
申请人： Stefano Marsili , Marc Tiebout , Andrea Bevilacqua , Stefano Dal Toso
发明人： Stefano Marsili , Marc Tiebout , Andrea Bevilacqua , Stefano Dal Toso
IPC分类号： H04B1/00
CPC分类号： H04B1/7136 , H03L7/06 , H04B2001/71362
摘要： Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.
摘要翻译：用于合成频率以用于快速跳跃无线通信系统的装置和系统。频率合成器包括多个振荡器，每个振荡器具有耦合到参考时钟频率信号的第一输入端，以及信号选择器，具有控制信号输入和多个参考时钟输入，每个参考时钟输入耦合到来自振荡器每个振荡器产生参考频率，其是参考时钟频率信号的参考时钟频率的谐波，并且信号选择器基于由控制信号输入提供的控制信号将参考时钟输入耦合到输出。

5. 发明申请

US20090088113A1 Fast Hopping Frequency Synthesizer 有权
标题翻译：快速跳频合成器
公开(公告)号：US20090088113A1
公开(公告)日：2009-04-02
申请号：US11863037
申请日：2007-09-27
申请人： Stefano Marsili , Marc Tiebout , Andrea Bevilacqua , Sterano Dal Toso
发明人： Stefano Marsili , Marc Tiebout , Andrea Bevilacqua , Sterano Dal Toso
IPC分类号： H04B1/06 , H03B27/00 , H03B5/08
CPC分类号： H04B1/7136 , H03L7/06 , H04B2001/71362
摘要： Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.
摘要翻译：用于合成频率以用于快速跳频无线通信系统的装置和系统。频率合成器包括多个振荡器，每个振荡器具有耦合到参考时钟频率信号的第一输入端，以及信号选择器，具有控制信号输入和多个参考时钟输入，每个参考时钟输入耦合到来自振荡器每个振荡器产生参考频率，其是参考时钟频率信号的参考时钟频率的谐波，并且信号选择器基于由控制信号输入提供的控制信号将参考时钟输入耦合到输出。

6. 发明授权

US07606538B2 Mixer circuit and method 有权
标题翻译：混频器电路及方法
公开(公告)号：US07606538B2
公开(公告)日：2009-10-20
申请号：US11487205
申请日：2006-07-14
申请人： Stefano Marsili , Marc Tiebout
发明人： Stefano Marsili , Marc Tiebout
IPC分类号： H04B1/04 , H04B17/00 , H03C1/62
CPC分类号： H04B1/0475 , H04B2001/0491
摘要： A mixer circuit includes a mixer having input terminals and an output terminal, to provide an output signal by mixing input signals, wherein the mixer exhibits leakage. The circuit also includes a signal generator coupled to one of the input terminals of the mixer to provide a correction signal, an up-conversion mixer coupled to the mixer to provide an up-converted signal by mixing a test signal with the output signal of the mixer, and a down-conversion mixer coupled to the up-conversion mixer to provide a down-converted signal by down-converting the up-converted signal. A signal detector is coupled to the down-conversion mixer and detects a spurious signal in the down-converted signal, the spurious signal indicating the leakage, and a control unit is coupled to the signal detector and the signal generator to control generation of the correction signal depending on the detected spurious signal to compensate the leakage.
摘要翻译：混频器电路包括具有输入端和输出端的混频器，通过混合输入信号提供输出信号，其中混频器显示泄漏。电路还包括耦合到混频器的一个输入端以提供校正信号的信号发生器，耦合到混频器的上转换混频器，通过将测试信号与混频器和耦合到上变频混频器的下变频混频器，通过下变频上变频信号来提供下变频信号。信号检测器耦合到下变频混频器并检测下变频信号中的寄生信号，指示泄漏的寄生信号，以及控制单元耦合到信号检测器和信号发生器以控制校正的产生信号取决于检测到的杂散信号以补偿泄漏。

7. 发明申请

US20080013755A1 Mixer circuit and method 有权
标题翻译：混频器电路及方法
公开(公告)号：US20080013755A1
公开(公告)日：2008-01-17
申请号：US11487205
申请日：2006-07-14
申请人： Stefano Marsili , Marc Tiebout
发明人： Stefano Marsili , Marc Tiebout
IPC分类号： H04B1/00
CPC分类号： H04B1/0475 , H04B2001/0491
摘要： A mixer circuit includes a mixer having input terminals and an output terminal, to provide an output signal by mixing input signals, wherein the mixer exhibits leakage. The circuit also includes a signal generator coupled to one of the input terminals of the mixer to provide a correction signal, an up-conversion mixer coupled to the mixer to provide an up-converted signal by mixing a test signal with the output signal of the mixer, and a down-conversion mixer coupled to the up-conversion mixer to provide a down-converted signal by down-converting the up-converted signal. A signal detector is coupled to the down-conversion mixer and detects a spurious signal in the down-converted signal, the spurious signal indicating the leakage, and a control unit is coupled to the signal detector and the signal generator to control generation of the correction signal depending on the detected spurious signal to compensate the leakage.
摘要翻译：混频器电路包括具有输入端和输出端的混频器，通过混合输入信号提供输出信号，其中混频器显示泄漏。电路还包括耦合到混频器的一个输入端以提供校正信号的信号发生器，耦合到混频器的上转换混频器，通过将测试信号与混频器和耦合到上变频混频器的下变频混频器，通过下变频上变频信号来提供下变频信号。信号检测器耦合到下变频混频器并检测下变频信号中的寄生信号，指示泄漏的寄生信号，以及控制单元耦合到信号检测器和信号发生器以控制校正的产生信号取决于检测到的杂散信号以补偿泄漏。

8. 发明授权

US08457176B2 Fast frequency-hopping transceiver and method 有权
标题翻译：快速跳频收发器和方法
公开(公告)号：US08457176B2
公开(公告)日：2013-06-04
申请号：US13309998
申请日：2011-12-02
申请人： Manfred Punzenberger , Stefano Marsili , Andreas Wiesbauer , Christoph Sandner , Yossi Erlich
发明人： Manfred Punzenberger , Stefano Marsili , Andreas Wiesbauer , Christoph Sandner , Yossi Erlich
IPC分类号： H04B1/713
CPC分类号： H04B1/71632 , H04B1/713 , H04L27/2601
摘要： A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.
摘要翻译：快速跳频收发器包括布置在第一芯片上的RF单元，第二芯片上的基带单元，布置在所述第一芯片和所述第二芯片之间的双向可操作数据和控制接口，其具有用于数据的至少一条数据线通信，用于控制数据通信的至少一个控制线和用于提供时钟信号的至少一个时钟线;在所述RF单元内实现的存储装置，其包含特定于接收到的某个频率的所有所需的芯片设置和/或传输数据是预期跳频序列的一部分。收发器还包括用于在建立所述数据通信的通信链路期间的初始化阶段期间对所述存储器装置进行编程的控制装置。

9. 发明授权

US07365662B2 DC-offset correction circuit for a communication system and method of correcting a DC-offset in a communication system 失效
标题翻译：用于通信系统的直流偏移校正电路和校正通信系统中的直流偏移的方法
公开(公告)号：US07365662B2
公开(公告)日：2008-04-29
申请号：US11492575
申请日：2006-07-25
申请人： Stefano Marsili , Raffaele Salerno , Yossi Erlich , Manfred Punzenberger , Andreas Wiesbauer
发明人： Stefano Marsili , Raffaele Salerno , Yossi Erlich , Manfred Punzenberger , Andreas Wiesbauer
IPC分类号： H03M1/06
CPC分类号： H04B1/30
摘要： A DC-offset correction circuit includes an analog circuit to generate a plurality of analog offset-correction signal values, each of which are assigned to a hop band. The analog circuit is coupled to a tap of an analog receiver chain and includes a first analog selector to select an analog offset-correction signal value, the selected analog offset correcting signal value being assigned to a current hop band. Further, the DC-offset correction circuit includes a combiner to combine a received signal with the selected analog offset-correction signal value and feed the analog receiver chain.
摘要翻译： DC偏移校正电路包括用于产生多个模拟偏移校正信号值的模拟电路，每个模拟偏移校正信号值被分配给跳频带。模拟电路耦合到模拟接收器链的抽头，并且包括第一模拟选择器以选择模拟偏移校正信号值，所选择的模拟偏移校正信号值被分配给当前跳频带。此外，DC偏移校正电路包括组合器，以将接收到的信号与所选择的模拟偏移校正信号值组合并馈送模拟接收器链。

10. 发明申请

US20060120435A1 Fast frequency-hopping transceiver and method 有权
公开(公告)号：US20060120435A1
公开(公告)日：2006-06-08
申请号：US11294213
申请日：2005-12-05
申请人： Manfred Punzenberger , Stefano Marsili , Andreas Wiesbauer , Christoph Sandner , Yossi Erlich
发明人： Manfred Punzenberger , Stefano Marsili , Andreas Wiesbauer , Christoph Sandner , Yossi Erlich
IPC分类号： H04B1/713
CPC分类号： H04B1/71632 , H04B1/713 , H04L27/2601
摘要： A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.

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