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1. 发明申请

US20110241086A1 ALUMINUM FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATE ELECTRODE STRUCTURES 有权
标题翻译：包含金属栅电极结构的半导体器件中的铝熔丝
公开(公告)号：US20110241086A1
公开(公告)日：2011-10-06
申请号：US12941595
申请日：2010-11-08
申请人： Andreas Kurz , Christoph Schwan , Jan Hoentschel
发明人： Andreas Kurz , Christoph Schwan , Jan Hoentschel
IPC分类号： H01L23/525 , H01L29/78 , H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system.
摘要翻译：在复杂的半导体器件中，可以通过使用铝材料作为用于在电子熔丝中诱导电迁移的有效金属的替代栅极方法来提供电子熔丝。电子熔断器可以形成在隔离结构上，从而提供电子熔断器与半导体材料和衬底材料的有效的热解耦，从而使得能够以大体积配置提供有效的电子保险丝，同时避免将熔丝引入金属化系统。

2. 发明授权

US08564089B2 Electronic fuse structure formed using a metal gate electrode material stack configuration 有权
标题翻译：使用金属栅电极材料堆叠配置形成的电子熔丝结构
公开(公告)号：US08564089B2
公开(公告)日：2013-10-22
申请号：US12941595
申请日：2010-11-08
申请人： Andreas Kurz , Christoph Schwan , Jan Hoentschel
发明人： Andreas Kurz , Christoph Schwan , Jan Hoentschel
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system.
摘要翻译：在复杂的半导体器件中，可以通过使用铝材料作为用于在电子熔丝中诱导电迁移的有效金属的替代栅极方法来提供电子熔丝。电子熔断器可以形成在隔离结构上，从而提供电子熔断器与半导体材料和衬底材料的有效的热解耦，从而使得能够以大体积配置提供有效的电子保险丝，同时避免将熔丝引入金属化系统。

3. 发明申请

US20110269278A1 Stress Memorization with Reduced Fringing Capacitance Based on Silicon Nitride in MOS Semiconductor Devices 有权
标题翻译：在MOS半导体器件中基于氮化硅的降低的起动电容的应力记忆
公开(公告)号：US20110269278A1
公开(公告)日：2011-11-03
申请号：US12963753
申请日：2010-12-09
申请人： Jan Hoentschel , Andreas Kurz , Uwe Griebenow , Thilo Scheiper
发明人： Jan Hoentschel , Andreas Kurz , Uwe Griebenow , Thilo Scheiper
IPC分类号： H01L21/8238 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/265 , H01L21/26506 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/4983 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7847
摘要： In sophisticated semiconductor devices, stress memorization techniques may be applied on the basis of a silicon nitride material, which may be subsequently modified into a low-k dielectric material in order to obtain low-k spacer elements, thereby enhancing performance of sophisticated semiconductor devices. The modification of the initial silicon nitride-based spacer material may be accomplished on the basis of an oxygen implantation process.
摘要翻译：在复杂的半导体器件中，可以在氮化硅材料的基础上施加应力记忆技术，氮化硅材料可随后被修改为低k电介质材料，以便获得低k间隔元件，从而提高复杂的半导体器件的性能。初始氮化硅基隔离材料的修改可以在氧注入工艺的基础上完成。

4. 发明申请

US20110266633A1 Semiconductor Device Comprising Metal Gates and Semiconductor Resistors Formed on the Basis of a Replacement Gate Approach 有权
标题翻译：包括金属栅极和半导体电阻的半导体器件以替代栅极方式形成
公开(公告)号：US20110266633A1
公开(公告)日：2011-11-03
申请号：US12963364
申请日：2010-12-08
申请人： Sven Beyer , Klaus Hempel , Roland Stejskal , Andy Wei , Thilo Scheiper , Andreas Kurz , Uwe Griebenow , Jan Hoentschel
发明人： Sven Beyer , Klaus Hempel , Roland Stejskal , Andy Wei , Thilo Scheiper , Andreas Kurz , Uwe Griebenow , Jan Hoentschel
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L23/5252 , H01L23/5256 , H01L27/0629 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches.
摘要翻译：在替代栅极方法中，可以在更换栅电极结构中的半导体材料时保留半导体材料或其非晶体管结构中的至少其重要部分，例如精密电阻器，电子熔丝等。为此，可以至少在去除栅电极结构中的半导体材料之前提供适当的介电材料，而不需要对建立的替代栅极方法进行显着的修改。

5. 发明授权

US08450163B2 Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach 有权
标题翻译：半导体器件包括基于替代栅极方法形成的金属栅极和半导体电阻器
公开(公告)号：US08450163B2
公开(公告)日：2013-05-28
申请号：US12963364
申请日：2010-12-08
申请人： Sven Beyer , Klaus Hempel , Roland Stejskal , Andy Wei , Thilo Scheiper , Andreas Kurz , Uwe Griebenow , Jan Hoentschel
发明人： Sven Beyer , Klaus Hempel , Roland Stejskal , Andy Wei , Thilo Scheiper , Andreas Kurz , Uwe Griebenow , Jan Hoentschel
IPC分类号： H01L21/338 , H01L21/20 , H01L21/337 , H01L23/62
CPC分类号： H01L23/5252 , H01L23/5256 , H01L27/0629 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches.
摘要翻译：在替代栅极方法中，可以在更换栅电极结构中的半导体材料时保留半导体材料或其非晶体管结构中的至少其重要部分，例如精密电阻器，电子熔丝等。为此，可以至少在去除栅电极结构中的半导体材料之前提供适当的介电材料，而不需要对建立的替代栅极方法进行显着的修改。

6. 发明授权

US08426266B2 Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices 有权
标题翻译：在MOS半导体器件中基于氮化硅的减少的边缘电容的应力记忆
公开(公告)号：US08426266B2
公开(公告)日：2013-04-23
申请号：US12963753
申请日：2010-12-09
申请人： Jan Hoentschel , Andreas Kurz , Uwe Griebenow , Thilo Scheiper
发明人： Jan Hoentschel , Andreas Kurz , Uwe Griebenow , Thilo Scheiper
IPC分类号： H01L21/8238
CPC分类号： H01L29/7833 , H01L21/265 , H01L21/26506 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/4983 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7847
摘要： In sophisticated semiconductor devices, stress memorization techniques may be applied on the basis of a silicon nitride material, which may be subsequently modified into a low-k dielectric material in order to obtain low-k spacer elements, thereby enhancing performance of sophisticated semiconductor devices. The modification of the initial silicon nitride-based spacer material may be accomplished on the basis of an oxygen implantation process.
摘要翻译：在复杂的半导体器件中，可以在氮化硅材料的基础上施加应力记忆技术，氮化硅材料可随后被修改为低k电介质材料，以便获得低k间隔元件，从而提高复杂的半导体器件的性能。初始氮化硅基隔离材料的修改可以在氧注入工艺的基础上完成。

7. 发明授权

US09449826B2 Graded well implantation for asymmetric transistors having reduced gate electrode pitches 有权
标题翻译：对具有减小的栅电极间距的不对称晶体管进行分级阱注入
公开(公告)号：US09449826B2
公开(公告)日：2016-09-20
申请号：US12692886
申请日：2010-01-25
申请人： G Robert Mulfinger , Andy Wei , Jan Hoentschel , Vassilios Papageorgiou
发明人： G Robert Mulfinger , Andy Wei , Jan Hoentschel , Vassilios Papageorgiou
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/266 , H01L21/265 , H01L29/66 , H01L29/78
CPC分类号： H01L21/266 , H01L21/2652 , H01L21/26586 , H01L21/823493 , H01L29/6659 , H01L29/7833
摘要： In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.
摘要翻译：在复杂的半导体器件中，可以在不对称阱注入的基础上获得不对称晶体管配置，同时避免倾斜的注入工艺。为此，可以形成渐变注入掩模，例如渐变抗蚀剂掩模，其在不对称晶体管的源极侧可能在漏极侧具有更高的离子阻挡能力。例如，可以在具有高度性能增益的非倾斜注入工艺的基础上获得不对称构造，并且可以不考虑所考虑的技术标准而实现。

8. 发明授权

US08962429B2 Integrated circuits with improved spacers and methods for fabricating same 有权
标题翻译：具有改进间隔物的集成电路及其制造方法
公开(公告)号：US08962429B2
公开(公告)日：2015-02-24
申请号：US13572343
申请日：2012-08-10
申请人： Stefan Flachowsky , Jan Hoentschel
发明人： Stefan Flachowsky , Jan Hoentschel
IPC分类号： H01L21/336
CPC分类号： H01L21/823418 , H01L21/823468
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes simultaneously shielding a shielded region of a semiconductor substrate and exposing a surface of the shielded region of the semiconductor substrate. An ion implantation is performed to form implant areas in a non-shielded region of the semiconductor substrate adjacent the shielded region. Also, the semiconductor substrate is silicided to form a silicided area in the shielded region of the semiconductor substrate.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个实施例中，制造集成电路的方法包括同时屏蔽半导体衬底的屏蔽区域并暴露半导体衬底的屏蔽区域的表面。执行离子注入以在与屏蔽区域相邻的半导体衬底的非屏蔽区域中形成注入区域。此外，半导体衬底被硅化以在半导体衬底的屏蔽区域中形成硅化区域。

9. 发明授权

US08872272B2 Stress enhanced CMOS circuits and methods for their manufacture 有权
标题翻译：应力增强CMOS电路及其制造方法
公开(公告)号：US08872272B2
公开(公告)日：2014-10-28
申请号：US13545624
申请日：2012-07-10
申请人： Stefan Flachowsky , Jan Hoentschel
发明人： Stefan Flachowsky , Jan Hoentschel
IPC分类号： H01L21/31 , H01L27/092
CPC分类号： H01L21/823807 , H01L27/092
摘要： A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit.
摘要翻译：制造应力增强型CMOS电路的方法包括以第一间距形成第一多个MOS晶体管，并以第二间距形成第二多个MOS晶体管。第二间距大于第一间距。该方法还包括沉积覆盖第一和第二多个MOS晶体管的单个应力衬垫。单应力衬垫是沉积在应力增强CMOS电路制造中的唯一应力衬垫。应力增强型CMOS电路包括以第一间距形成的第一多个MOS晶体管和以第二间距形成的第二多个MOS晶体管。第二间距大于第一间距。电路还包括覆盖第一和第二多个MOS晶体管的单个应力衬垫。单应力衬垫是在应力增强CMOS电路上形成的唯一应力衬垫。

10. 发明授权

US08822298B2 Performance enhancement in transistors by reducing the recessing of active regions and removing spacers 有权
标题翻译：通过减少活性区域的凹陷和去除间隔物来提高晶体管的性能
公开(公告)号：US08822298B2
公开(公告)日：2014-09-02
申请号：US13421242
申请日：2012-03-15
申请人： Stefan Flachowsky , Jan Hoentschel
发明人： Stefan Flachowsky , Jan Hoentschel
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823425 , H01L21/823468 , H01L21/823814 , H01L21/823864
摘要： Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.
摘要翻译：可以基于优良的工艺顺序形成用于半导体器件的复杂晶体管，其中可以获得紧密间隔的栅极电极结构之间的增加的空间，同时在有源区域中减少材料损耗。为此，省略了通常用于横向成形漏极和源极延伸区域的偏移间隔物，并且用于深度漏极和源极区域的间隔物可以被完全去除。

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