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1. 发明授权

US07977225B2 Reducing implant degradation in tilted implantations by shifting implantation masks 有权
标题翻译：通过移植植入掩模减少倾斜植入中的植入物退化
公开(公告)号：US07977225B2
公开(公告)日：2011-07-12
申请号：US12417978
申请日：2009-04-03
申请人： Andre Poock , Jan Hoentschel
发明人： Andre Poock , Jan Hoentschel
IPC分类号： H01L21/425
CPC分类号： H01L21/823814 , H01L21/823807 , Y10S438/942 , Y10S438/944
摘要： In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks.
摘要翻译：在非常规模的半导体器件中，可以通过提供用于被掩模的晶体管元件的不对称掩模布置，在倾斜注入工艺期间，在倾斜注入工艺的基础上，增加抗蚀剂高度和/或倾斜角度来建立非对称晶体管配置。为此，可以将注入掩模移动适当的量，以便增强掩模晶体管的总体阻塞效应，同时减少非掩蔽晶体管的注入掩模的任何阴影效应。注入掩模的移位可以通过基于“移位的”目标值执行自动对准过程或通过提供不对称布置的光刻掩模来实现。

2. 发明申请

US20090325355A1 REDUCING IMPLANT DEGRADATION IN TILTED IMPLANTATIONS BY SHIFTING IMPLANTATION MASKS 有权
标题翻译：通过移植植入面减少植入植被的植入降解
公开(公告)号：US20090325355A1
公开(公告)日：2009-12-31
申请号：US12417978
申请日：2009-04-03
申请人： Andre Poock , Jan Hoentschel
发明人： Andre Poock , Jan Hoentschel
IPC分类号： H01L21/426 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , Y10S438/942 , Y10S438/944
摘要： In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks.
摘要翻译：在非常规模的半导体器件中，可以通过提供用于被掩模的晶体管元件的不对称掩模布置，在倾斜注入工艺期间，在倾斜注入工艺的基础上，增加抗蚀剂高度和/或倾斜角度来建立非对称晶体管配置。为此，可以将注入掩模移动适当的量，以便增强掩模晶体管的总体阻塞效应，同时减少非掩蔽晶体管的注入掩模的任何阴影效应。注入掩模的移位可以通过基于“移位的”目标值执行自动对准过程或通过提供不对称布置的光刻掩模来实现。

3. 发明授权

US09449826B2 Graded well implantation for asymmetric transistors having reduced gate electrode pitches 有权
标题翻译：对具有减小的栅电极间距的不对称晶体管进行分级阱注入
公开(公告)号：US09449826B2
公开(公告)日：2016-09-20
申请号：US12692886
申请日：2010-01-25
申请人： G Robert Mulfinger , Andy Wei , Jan Hoentschel , Vassilios Papageorgiou
发明人： G Robert Mulfinger , Andy Wei , Jan Hoentschel , Vassilios Papageorgiou
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/266 , H01L21/265 , H01L29/66 , H01L29/78
CPC分类号： H01L21/266 , H01L21/2652 , H01L21/26586 , H01L21/823493 , H01L29/6659 , H01L29/7833
摘要： In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.
摘要翻译：在复杂的半导体器件中，可以在不对称阱注入的基础上获得不对称晶体管配置，同时避免倾斜的注入工艺。为此，可以形成渐变注入掩模，例如渐变抗蚀剂掩模，其在不对称晶体管的源极侧可能在漏极侧具有更高的离子阻挡能力。例如，可以在具有高度性能增益的非倾斜注入工艺的基础上获得不对称构造，并且可以不考虑所考虑的技术标准而实现。

4. 发明授权

US08962429B2 Integrated circuits with improved spacers and methods for fabricating same 有权
标题翻译：具有改进间隔物的集成电路及其制造方法
公开(公告)号：US08962429B2
公开(公告)日：2015-02-24
申请号：US13572343
申请日：2012-08-10
申请人： Stefan Flachowsky , Jan Hoentschel
发明人： Stefan Flachowsky , Jan Hoentschel
IPC分类号： H01L21/336
CPC分类号： H01L21/823418 , H01L21/823468
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes simultaneously shielding a shielded region of a semiconductor substrate and exposing a surface of the shielded region of the semiconductor substrate. An ion implantation is performed to form implant areas in a non-shielded region of the semiconductor substrate adjacent the shielded region. Also, the semiconductor substrate is silicided to form a silicided area in the shielded region of the semiconductor substrate.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个实施例中，制造集成电路的方法包括同时屏蔽半导体衬底的屏蔽区域并暴露半导体衬底的屏蔽区域的表面。执行离子注入以在与屏蔽区域相邻的半导体衬底的非屏蔽区域中形成注入区域。此外，半导体衬底被硅化以在半导体衬底的屏蔽区域中形成硅化区域。

5. 发明授权

US08872272B2 Stress enhanced CMOS circuits and methods for their manufacture 有权
标题翻译：应力增强CMOS电路及其制造方法
公开(公告)号：US08872272B2
公开(公告)日：2014-10-28
申请号：US13545624
申请日：2012-07-10
申请人： Stefan Flachowsky , Jan Hoentschel
发明人： Stefan Flachowsky , Jan Hoentschel
IPC分类号： H01L21/31 , H01L27/092
CPC分类号： H01L21/823807 , H01L27/092
摘要： A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit.
摘要翻译：制造应力增强型CMOS电路的方法包括以第一间距形成第一多个MOS晶体管，并以第二间距形成第二多个MOS晶体管。第二间距大于第一间距。该方法还包括沉积覆盖第一和第二多个MOS晶体管的单个应力衬垫。单应力衬垫是沉积在应力增强CMOS电路制造中的唯一应力衬垫。应力增强型CMOS电路包括以第一间距形成的第一多个MOS晶体管和以第二间距形成的第二多个MOS晶体管。第二间距大于第一间距。电路还包括覆盖第一和第二多个MOS晶体管的单个应力衬垫。单应力衬垫是在应力增强CMOS电路上形成的唯一应力衬垫。

6. 发明授权

US08822298B2 Performance enhancement in transistors by reducing the recessing of active regions and removing spacers 有权
标题翻译：通过减少活性区域的凹陷和去除间隔物来提高晶体管的性能
公开(公告)号：US08822298B2
公开(公告)日：2014-09-02
申请号：US13421242
申请日：2012-03-15
申请人： Stefan Flachowsky , Jan Hoentschel
发明人： Stefan Flachowsky , Jan Hoentschel
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823425 , H01L21/823468 , H01L21/823814 , H01L21/823864
摘要： Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.
摘要翻译：可以基于优良的工艺顺序形成用于半导体器件的复杂晶体管，其中可以获得紧密间隔的栅极电极结构之间的增加的空间，同时在有源区域中减少材料损耗。为此，省略了通常用于横向成形漏极和源极延伸区域的偏移间隔物，并且用于深度漏极和源极区域的间隔物可以被完全去除。

7. 发明授权

US08809151B2 Transistor comprising an embedded sigma shaped sequentially formed semiconductor alloy 有权
标题翻译：晶体管包括嵌入式西格玛顺序形成的半导体合金
公开(公告)号：US08809151B2
公开(公告)日：2014-08-19
申请号：US13232571
申请日：2011-09-14
申请人： Stefan Flachowsky , Stephan-Detlef Kronholz , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Stephan-Detlef Kronholz , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L29/165
CPC分类号： H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials.
摘要翻译：在复杂的晶体管中，可以在漏极区域和源极区域中顺序提供诸如应变诱导半导体材料的特殊设计的半导体材料，从而使得生长的半导体材料的显着程度的横向延伸，而不会危害机械完整性晶体管在其处理期间。例如，可以在依次提供的嵌入式半导体材料的基础上提供具有不同漏极和源极侧的半导体器件。

8. 发明授权

US08772878B2 Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material 有权
标题翻译：基于硅/碳材料的PMOS和NMOS晶体管的性能增强
公开(公告)号：US08772878B2
公开(公告)日：2014-07-08
申请号：US13362763
申请日：2012-01-31
申请人： Jan Hoentschel , Vassilios Papageorgiou , Belinda Hannon
发明人： Jan Hoentschel , Vassilios Papageorgiou , Belinda Hannon
IPC分类号： H01L21/70
CPC分类号： H01L27/092 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/1033 , H01L29/1083 , H01L29/1608 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7847 , H01L29/7848
摘要： A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.
摘要翻译：可以在适当的制造方案的基础上，以不同导电类型的晶体管提供硅/锗材料和硅/碳材料，而不会不利地导致整个工艺的复杂性。此外，在形成相应的应变半导体合金之前，可以通过空腔的暴露的表面区域提供适当的注入物质，从而另外有助于提高总体晶体管性能。在其它实施例中，硅/碳材料可以形成在P沟道晶体管和N沟道晶体管中，而相应的拉伸应变分量可以通过在P沟道晶体管中的应力存储技术过度补偿。因此，可以将诸如增强P沟道晶体管的整体掺杂物分布的碳物质的有益效果与有效的应变分量组合，同时可以实现增强的整体工艺均匀性。

9. 发明申请

US20130320450A1 MIDDLE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS 有权
标题翻译：使用硅氧烷封装，早期黑曜石和延伸植入的28 NM低功率/高性能技术的PMOS器件的中间现场拨号信号连接
公开(公告)号：US20130320450A1
公开(公告)日：2013-12-05
申请号：US13482410
申请日：2012-05-29
申请人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
发明人： Jan Hoentschel , Shiang Yang Ong , Stefan Flachowsky , Thilo Scheiper
IPC分类号： H01L27/088 , H01L21/8238 , H01L21/336
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/0883 , H01L29/0847 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiO2 cap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.
摘要翻译：提供具有PMOS eSiGe源极/漏极区域的HKMG器件。实施例包括在衬底上形成第一和第二HKMG栅极堆叠，每个包括SiO 2盖，在第一HKMG栅极堆叠的相对侧形成延伸区域，在HKMG栅极堆叠的每一侧上形成氮化物衬垫和氧化物间隔物; 在第二个HKMG门堆栈上形成硬掩模; 在第一HKMG栅极堆叠的相对侧形成eSiGe，去除硬掩模，在第一和第二HKMG栅极堆叠中的每一个的氧化物间隔物上形成共形衬垫和氮化物间隔物，并在第二HKMG栅极叠层的相对侧形成深的源极/漏极区域第二个HKMG门栈。

10. 发明申请

US20130270645A1 WORKFUNCTION METAL STACKS FOR A FINAL METAL GATE 有权
标题翻译：用于最终金属门的功能金属堆叠
公开(公告)号：US20130270645A1
公开(公告)日：2013-10-17
申请号：US13445475
申请日：2012-04-12
申请人： Thilo Scheiper , Jan Hoentschel
发明人： Thilo Scheiper , Jan Hoentschel
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842
摘要： Transistor devices are formed with a pMOS and an nMOS workfunction stack of substantially equal thickness after gate patterning. Embodiments include forming n-type and p-type areas in a substrate, forming a pMOS workfunction metal stack layer on both areas, forming a hardmask layer on the pMOS workfunction metal stack layer on the n-type area, removing the pMOS workfunction metal stack layer from the p-type area, forming an nMOS workfunction metal stack layer on the p-type area and on the hardmask layer, and removing the nMOS workfunction metal stack layer from the hardmask layer.
摘要翻译：在栅极图案化之后，晶体管器件由具有基本相等厚度的pMOS和nMOS功函数堆叠形成。实施例包括在基板中形成n型和p型区域，在两个区域上形成pMOS功函数金属堆叠层，在n型区域上的pMOS功函数金属堆叠层上形成硬掩模层，去除pMOS功函数金属堆层，在p型区域和硬掩模层上形成nMOS功函数金属堆叠层，并从硬掩模层去除nMOS功函数金属堆叠层。

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