专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10402526B2 Integrated system of PDN implementation and digital co-synthesis 有权
公开(公告)号：US10402526B2
公开(公告)日：2019-09-03
申请号：US15174877
申请日：2016-06-06
申请人： Taner Dosluoglu , Anatoly Gelman
发明人： Taner Dosluoglu , Anatoly Gelman
IPC分类号： G06F17/50
摘要： Design of a power delivery network (PDN) is integrated with a digital logic design flow.

2. 发明申请

US20190265769A1 METHOD AND APPARATUS FOR IMPROVING INTEGRITY OF PROCESSOR VOLTAGE SUPPLY WITH SUPPORT FOR DVFS 审中-公开
公开(公告)号：US20190265769A1
公开(公告)日：2019-08-29
申请号：US16286041
申请日：2019-02-26
申请人： Anatoly Gelman , Taner Dosluoglu
发明人： Anatoly Gelman , Taner Dosluoglu
IPC分类号： G06F1/30 , H03K5/01 , H03H7/06
摘要： Dedicated circuitry may monitor a processor supply voltage and provide additional power on a temporary nano-second scale basis to the processor when the supply voltage drops below predetermined levels. This may be done without explicit knowledge of a commanded supply voltage level for the processor.

3. 发明申请

US20180364285A1 VOLTAGE REGULATOR WITH TIME-AWARE CURRENT REPORTING 审中-公开
公开(公告)号：US20180364285A1
公开(公告)日：2018-12-20
申请号：US16009059
申请日：2018-06-14
申请人： Anatoly Gelman , Taner Dosluoglu
发明人： Anatoly Gelman , Taner Dosluoglu
IPC分类号： G01R19/25 , H02M3/158
摘要： Systems and methods for providing an indication of an output current of a voltage regulator applied to a load at an indicated time to a processor. An indication of the output current of a voltage regulator is determined in response to a clock signal received from a clock source and a frame number of a frame is determined from the clock source. The indication of the current output and the frame number of the associated frame are provided to the processor.

4. 发明申请

US20160357882A1 INTEGRATED SYSTEM OF PDN IMPLEMENTATION AND DIGITAL CO-SYNTHESIS 审中-公开
标题翻译： PDN实现和数字合成综合系统
公开(公告)号：US20160357882A1
公开(公告)日：2016-12-08
申请号：US15174877
申请日：2016-06-06
申请人： Taner Dosluoglu , Anatoly Gelman
发明人： Taner Dosluoglu , Anatoly Gelman
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5036 , G06F17/5068 , G06F2217/78
摘要： Design of a power delivery network (PDN) is integrated with a digital logic design flow.
摘要翻译：功率传输网络（PDN）的设计与数字逻辑设计流程集成。

5. 发明申请

US20210050789A1 CONFIGURABLE-SPEED MULTI-PHASE DC/DC SWITCHING CONVERTER WITH HYSTERESIS-LESS PHASE SHEDDING AND INDUCTOR BYPASS 有权
公开(公告)号：US20210050789A1
公开(公告)日：2021-02-18
申请号：US16992781
申请日：2020-08-13
申请人： Anatoly Gelman , Taner Dosluoglu , Bertrand Diotte
发明人： Anatoly Gelman , Taner Dosluoglu , Bertrand Diotte
IPC分类号： H02M3/158 , G05F1/59 , H03K5/24
摘要： Some embodiments provide a multi-phase DC/DC switching converter in which each of the phases are controlled using a common comparator for comparing an output voltage of the switching converter and a reference voltage, with in some embodiments each of the phases including a bypass switch for coupling ends of an output inductor of the switching converter. Some embodiments provide a multi-phase DC/DC switching converter in which some of the phases are operated with clock signals having frequencies different than clock signals used for operating others of the phases. Some embodiments provide a multi-phase DC/DC switching converter in which some of the phases include inductors having inductances different than inductances for inductors of others of the phases.

6. 发明申请

US20190265779A1 METHOD AND APPARATUS FOR IMPROVING INTEGRITY OF PROCESSOR VOLTAGE SUPPLY WITH OVERSHOOT MITIGATION AND SUPPORT FOR DVFS 审中-公开
公开(公告)号：US20190265779A1
公开(公告)日：2019-08-29
申请号：US16286138
申请日：2019-02-26
申请人： Anatoly Gelman , Taner Dosluoglu
发明人： Anatoly Gelman , Taner Dosluoglu
IPC分类号： G06F1/3296 , G06F1/12 , G06F1/324 , G06F1/28 , G06F1/08
摘要： Circuitry may monitor a processor supply voltage and pull power from the processor supply on a temporary basis when the supply voltage rises above predetermined levels. In some embodiments this may be done without explicit knowledge of a commanded supply voltage level for the processor.

7. 发明申请

US20120154648A1 SIMULTANEOUS GLOBAL SHUTTER AND CORRELATED DOUBLE SAMPLING READ OUT IN MULTIPLE PHOTOSENSOR PIXELS 有权
标题翻译：同时全球快门和相关双重采样读取多个光电子像素
公开(公告)号：US20120154648A1
公开(公告)日：2012-06-21
申请号：US13403862
申请日：2012-02-23
申请人： Taner Dosluoglu
发明人： Taner Dosluoglu
IPC分类号： H04N9/04
CPC分类号： H04N5/3575 , H04N5/353 , H04N5/3532
摘要： An apparatus controls operation of an array of color multiple sensor pixel image sensors to provide a global shuttering for one half of the color multiple sensor pixel image sensors and a rolling shuttering for all color multiple sensor pixel image sensors of the array. The apparatus includes a row control circuit and a column clamp, sample, and hold circuit. The row control circuit generates the necessary reset control signals, transfer gating signals, and row selecting signals for providing the global shuttering and the rolling shuttering color multiple sensor pixel image sensors. The column clamp, sample and hold circuit generates an output signal representative of a number of photons impinging upon each color multiple sensor pixel image sensor of the row of selected color multiple sensor pixel image sensors. The control apparatus further includes an analog to digital converter which converts the read out signal to a digital image signal.
摘要翻译：一种设备控制彩色多传感器像素图像传感器阵列的操作，以为彩色多传感器像素图像传感器的一半提供全局快门，以及用于阵列的所有彩色多传感器像素图像传感器的滚动快门。该装置包括行控制电路和列钳，采样保持电路。行控制电路产生必要的复位控制信号，传送选通信号和行选择信号，以提供全局快门和滚动快门彩色多传感器像素图像传感器。柱夹，采样和保持电路产生表示入射到所选择的彩色多传感器像素图像传感器行中的每个彩色多传感器像素图像传感器的光子数量的输出信号。控制装置还包括将读出的信号转换为数字图像信号的模数转换器。

8. 发明授权

US07515183B2 Column averaging/row binning circuit for image sensor resolution adjustment in lower intensity light environment 有权
标题翻译：列平均/行分类电路，用于在较低强度的光环境中进行图像传感器分辨率调整
公开(公告)号：US07515183B2
公开(公告)日：2009-04-07
申请号：US10997383
申请日：2004-11-24
申请人： Guang Yang , Taner Dosluoglu
发明人： Guang Yang , Taner Dosluoglu
IPC分类号： H04N5/217 , H04N3/14 , H04N5/335
CPC分类号： H04N9/045 , H04N5/347 , H04N5/374
摘要： A photo-sensor image resolution adjustment apparatus is in communication with an array of image photo-sensors that are organized in columns and rows and have multiple sensor types arranged in a pattern such as a Bayer pattern to detect light. The photo-sensor image resolution adjustment apparatus has a photo-sensor array decimation circuit to partition the array of image photo-sensors into a plurality of sub-groups. A column averaging circuit averages the light conversion electrical signals from common color photo-sensors within the sub-groups. A row averaging circuit averages the common color adjacent light conversion electrical signals from color adjacent rows within the sub-groups in high light intensity condition. In low light conditions, a row binning circuit integrates the common color adjacent light conversion electrical signals from color adjacent rows within the sub-groups.
摘要翻译：光传感器图像分辨率调节装置与以列和行组织的图像光传感器阵列通信，并且具有以诸如Bayer图案的图案排列以检测光的多个传感器类型。光传感器图像分辨率调节装置具有光传感器阵列抽取电路，以将图像光传感器阵列分割成多个子组。列平均电路对子组内常用彩色光电传感器的光转换电信号进行平均。行平均电路在高光强度条件下对来自子组内的颜色相邻行的相邻光转换电信号的常用颜色进行平均。在低光条件下，行分组电路将来自子组内的颜色相邻行的相邻光转换电信号的公共颜色相集成。

9. 发明授权

US07336530B2 CMOS pixel with dual gate PMOS 有权
标题翻译：具有双栅极PMOS的CMOS像素
公开(公告)号：US07336530B2
公开(公告)日：2008-02-26
申请号：US11508354
申请日：2006-08-23
申请人： Taner Dosluoglu , Nathaniel Joseph McCaffrey
发明人： Taner Dosluoglu , Nathaniel Joseph McCaffrey
IPC分类号： G11C11/34 , H01L21/8238
CPC分类号： H01L27/14609 , H01L27/14632 , H01L27/14643 , H01L31/112
摘要： A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P− type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N− well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N− well potential so that they remain reverse biased with respect to the N− well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N− well forms a second gate for the dual gate PMOS transistor since the potential of the N− well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible. The circuit can be expanded to form two PMOS transistors sharing a common drain in the N− well.
摘要翻译：具有双栅极PMOS的像素电路通过在N阱中形成两个P + +区形成。 N＆lt;＆gt; - 孔是在P + - SUP型衬底中。两个P + SUP区域形成PMOS晶体管的源极和漏极。形成在N阱内的PMOS晶体管不会影响光电荷的收集，只要PMOS晶体管的源极和漏极电位被设置在比N - 阱电位，使得它们相对于N 阱保持反向偏置。用于形成源极和漏极区域的一个P + SUP区域可用于在读取该像素以准备下一个累积光电荷循环之后复位像素。由于NΩ阱12的电位影响PMOS晶体管的沟道的导电性，因此N阱构成了双栅极PMOS晶体管的第二栅极。添加两个NMOS晶体管使读出信号能够存储在NMOS晶体管之一的栅极处，从而使快照成像器成为可能。该电路可以扩展以形成在N阱中共享一个共同漏极的两个PMOS晶体管。

10. 发明授权

US07265397B1 CCD imager constructed with CMOS fabrication techniques and back illuminated imager with improved light capture 有权
标题翻译：采用CMOS制造技术构建的CCD成像仪和具有改进的光捕获功能的背光照明成像仪
公开(公告)号：US07265397B1
公开(公告)日：2007-09-04
申请号：US09942835
申请日：2001-08-30
申请人： John Robertson Tower , Peter Alan Levine , Pradyumna Kumar Swain , Nathaniel Joseph McCaffrey , Taner Dosluoglu
发明人： John Robertson Tower , Peter Alan Levine , Pradyumna Kumar Swain , Nathaniel Joseph McCaffrey , Taner Dosluoglu
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H01L27/14806 , H01L27/1464 , H01L27/14689 , H04N5/335 , H04N5/372 , H04N5/37455
摘要： An optical sensor circuit for generating signals corresponding to received photoelectrons is formed on a single monolithic substrate and includes a charge coupled device (CCD) array. The array is formed of a plurality of pixels constructed by a standard CMOS process. Each pixel is formed of at least one charge well of minority carriers and a gate oxide layer overlaying the at least one charge well. At least two spaced gate electrodes corresponding in position to the at least two charge wells overlays the gate oxide layer. The space between adjacent electrodes defines a gap to transfer charge between adjacent ones of at the least two spaced gate electrodes and the gap is stabilized. A back-illuminated imager is also described in which photocarriers are diverted from devices integrated with the pixel by a PN junction formed in the pixel structure.
摘要翻译：用于产生与接收的光电子相对应的信号的光学传感器电路形成在单个单片基板上，并且包括电荷耦合器件（CCD）阵列。阵列由通过标准CMOS工艺构成的多个像素形成。每个像素由少数载流子的至少一个电荷阱和覆盖至少一个电荷阱的栅极氧化物层形成。至少两个对应于位于至少两个电荷阱的位置的间隔开的栅极覆盖栅极氧化物层。相邻电极之间的空间限定了在至少两个间隔开的栅极电极之间的相邻电极之间传输电荷的间隙，并且间隙被稳定。还描述了背照光成像器，其中光载流子通过形成在像素结构中的PN结从与像素集成的器件转移。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式