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1. 发明授权

US07494893B1 Identifying yield-relevant process parameters in integrated circuit device fabrication processes 失效
标题翻译：识别集成电路器件制造工艺中的屈服相关工艺参数
公开(公告)号：US07494893B1
公开(公告)日：2009-02-24
申请号：US11654391
申请日：2007-01-17
申请人： Anand Inani , Brian E. Stine , Marci Yi-Ting Liao , Senthil Arthanari , Michael V. Williamson , Spencer B. Graves , Guanyuan M. Yu
发明人： Anand Inani , Brian E. Stine , Marci Yi-Ting Liao , Senthil Arthanari , Michael V. Williamson , Spencer B. Graves , Guanyuan M. Yu
IPC分类号： H01L21/76
CPC分类号： G05B19/41875 , G05B2219/32177 , G05B2219/45031 , Y02P90/22 , Y02P90/86
摘要： In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process module. The test structures may be tested to obtain defectivity data. Tool process parameters may be monitored and collected as process tool data. Other information about the wafers, such as metrology data and product layout attribute, may also be collected. A model describing the relationship between the defectivity data and process tool data may be created and thereafter used to relate the process tool data to a yield of the process module. The model may initially be an initial model using process tool data from a limited number of test wafers that contain test structures. The model may also be an expanded model using process tool data from product wafers containing embedded test structures in areas with no product devices.
摘要翻译：在一个实施例中，处理晶片以在晶片中构建测试结构。可以在属于处理模块的工艺步骤的工具中处理晶片。可以测试测试结构以获得缺陷数据。工具过程参数可以作为过程工具数据进行监控和收集。还可以收集关于晶片的其它信息，例如测量数据和产品布局属性。可以创建描述缺陷率数据和处理工具数据之间的关系的模型，然后用于将过程工具数据与处理模块的收益相关联。该模型可以初始化为使用来自有限数量的包含测试结构的测试晶片的工艺工具数据的初始模型。该模型还可以是使用具有无产品设备的区域中包含嵌入式测试结构的产品晶圆的工艺工具数据的扩展模型。

2. 发明申请

US20080312875A1 Monitoring and control of integrated circuit device fabrication processes 审中-公开
标题翻译：集成电路器件制造工艺的监控
公开(公告)号：US20080312875A1
公开(公告)日：2008-12-18
申请号：US11811802
申请日：2007-06-12
申请人： Guanyuan M. Yu , Michael V. Williamson , Spencer B. Graves
发明人： Guanyuan M. Yu , Michael V. Williamson , Spencer B. Graves
IPC分类号： G06F19/00
CPC分类号： G05B19/41875 , G05B2219/32187 , G05B2219/32188 , G05B2219/32194 , Y02P90/22 , Y02P90/265 , Y02P90/86
摘要： An integrated circuit (IC) device fabrication process may be monitored by processing product wafers to fabricate product IC devices, collecting process tool data from tools used to fabricate the product IC devices, and testing the product IC devices. To predict and monitor yield, the process tool data collected during processing and the defectivity data from testing the product IC devices may be input to a yield model that also takes into account design information particular to the product devices. The design information may comprise layout attributes of the product devices. The yield model may be generated from a defectivity model created by processing test wafers to fabricate test structures, collecting process tool data from tools used to fabricate the test structures, and testing the test structures. The test structures may have varying layout attributes to cover a design space allowed by design rules for particular product IC devices.
摘要翻译：集成电路（IC）器件制造过程可以通过处理产品晶片来制造产品IC器件，从用于制造产品IC器件的工具收集工艺工具数据以及测试产品IC器件来监控。为了预测和监测产量，可以将处理期间收集的过程工具数据和来自测试产品IC器件的缺陷数据输入到也考虑产品设备特有的设计信息的产量模型。设计信息可以包括产品设备的布局属性。产量模型可以从通过处理测试晶片产生的缺陷模型产生，以制造测试结构，从用于制造测试结构的工具收集过程工具数据，以及测试测试结构。测试结构可以具有不同的布局属性以覆盖特定产品IC设备的设计规则允许的设计空间。

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