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1. 发明授权

US07081672B1 Substrate via layout to improve bias humidity testing reliability 有权
标题翻译：基板通过布局改善偏差湿度测试的可靠性
公开(公告)号：US07081672B1
公开(公告)日：2006-07-25
申请号：US11073802
申请日：2005-03-07
申请人： Anand Govind , Aritharan Thurairajaratnam , Farshad Ghahghahi
发明人： Anand Govind , Aritharan Thurairajaratnam , Farshad Ghahghahi
IPC分类号： H01L23/34
CPC分类号： H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H05K1/0219 , H05K1/0222 , H05K1/0254 , H05K1/0263 , H05K1/0366 , H05K1/115 , H05K3/4602 , H05K2201/029 , H05K2201/09536 , H05K2201/09609 , H01L2924/00 , H01L2224/0401
摘要： A substrate is provided, which has a pattern of voltage supply vias extending through at least a portion of the substrate. Each of a plurality of the voltage supply vias is surrounded by four of the voltage supply vias of a same polarity in four orthogonal directions and by four voltage supply vias of an opposite polarity in four diagonal directions.
摘要翻译：提供了一种衬底，其具有延伸通过衬底的至少一部分的电压供给通孔的图案。多个电压供给通路中的每一个由四个正交方向上的相同极性的四个电压供给通孔和四个对角线方向上具有相反极性的四个电压供给通路围绕。

2. 发明授权

US06946866B2 Measurement of package interconnect impedance using tester and supporting tester 失效
标题翻译：使用测试仪和支持测试仪测量封装互连阻抗
公开(公告)号：US06946866B2
公开(公告)日：2005-09-20
申请号：US10620057
申请日：2003-07-15
申请人： Aritharan Thurairajaratnam , Mohan Nagar , Anand Govind , Farshad Ghahghahi
发明人： Aritharan Thurairajaratnam , Mohan Nagar , Anand Govind , Farshad Ghahghahi
IPC分类号： G01R31/28 , G01R31/02 , G01R31/11
CPC分类号： G01R31/2886
摘要： A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i.e., package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.
摘要翻译：来自测试仪的测试仪头用于安装探针卡。 DUT /负载板具有被配置为保持衬底的插座。探针卡的探头引脚与基板上的凸点焊盘接触。来自DUT /负载板的信号线馈送到测试仪，测试仪连接到具有快速上升时间信号头的DSO。在测试期间，使用DSO将信号发射到连接到测试头的同轴电缆。发射信号和反射信号由DSO捕获，然后送入测试仪。使用该数据，后处理软件用于获得被测器件（即，封装）的互连阻抗与时间的关系。该方法和设备可以与倒装芯片和线接合产品一起使用。

3. 发明授权

US06825066B2 Stiffener design 有权
标题翻译：加固设计
公开(公告)号：US06825066B2
公开(公告)日：2004-11-30
申请号：US10308310
申请日：2002-12-03
申请人： Yogendra Ranade , Anand Govind , Kumar Nagarajan , Farshad Ghahghahi , Aritharan Thurairajaratnam
发明人： Yogendra Ranade , Anand Govind , Kumar Nagarajan , Farshad Ghahghahi , Aritharan Thurairajaratnam
IPC分类号： H01L2144
CPC分类号： H01L23/04 , H01L23/50 , H01L25/165 , H01L2924/0002 , H01L2924/1433 , H01L2924/00
摘要： A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses. Because the major interior apertures does not need to be large enough to fit both the monolithic integrated circuit and the secondary circuit structure, there is more stiffener material available to provide structural support than there would be if the major interior aperture was large enough to fit both the monolithic integrated circuit and the secondary circuit structure.
摘要翻译：用于加强封装集成电路的加强件。加强件包括刚性平面元件，其具有用于结合到封装基板的第一表面。刚性平面元件形成用于在集成电路的所有侧面上接收和围绕集成电路的主要内部孔。刚性平面元件还形成次要内孔，用于在次级电路结构的至少三侧上接收和围绕次级电路结构。以这种方式，加强件提供对集成电路封装的结构支撑，其降低并优选地消除了衬底封装在其加热并经受其它应力时的扭曲和翘曲。因为主要内部孔径不需要足够大以适合单片集成电路和次级电路结构，所以有更多的加强材料可用于提供结构支撑，如果主要内部孔径足够大以适合于两者单片集成电路和二次电路结构。

4. 发明授权

US06531932B1 Microstrip package having optimized signal line impedance control 有权
标题翻译：微带封装具有优化的信号线阻抗控制
公开(公告)号：US06531932B1
公开(公告)日：2003-03-11
申请号：US09894210
申请日：2001-06-27
申请人： Anand Govind , Farshad Ghahghahi , Aritharan Thurairajaratnam
发明人： Anand Govind , Farshad Ghahghahi , Aritharan Thurairajaratnam
IPC分类号： H01P308
CPC分类号： H01P3/084 , H01L2224/16225 , H01L2224/32225 , H01L2224/73253 , H01L2924/15311 , H01P3/088
摘要： A method for fabricating a microstrip package to optimize signal trace impedance control is disclosed. The method includes patterning a plurality of signal traces on a multilayer substrate, and patterning a plurality of guard traces on the multilayer substrate, that are interspersed alternately among the signal traces to provide noise shielding between the signal traces. In a further embodiment, the traces are patterned on the substrate with a width that is adjusted at different locations based on the presence the guard traces to enable the package to meet a particular impedance requirement.
摘要翻译：公开了一种用于制造微带封装以优化信号迹线阻抗控制的方法。该方法包括在多层衬底上图形化多条信号迹线，以及对多层衬底上的多条保护迹线进行构图，其中交替地在信号迹线之间散布以提供信号迹线之间的噪声屏蔽。在另一个实施例中，迹线在衬底上被图案化，其宽度基于保护迹线的存在而被调整到不同的位置，以使封装能够满足特定的阻抗要求。

5. 发明授权

US06459049B1 High density signal routing 有权
标题翻译：高密度信号路由
公开(公告)号：US06459049B1
公开(公告)日：2002-10-01
申请号：US09885299
申请日：2001-06-20
申请人： Leah M. Miller , Farshad Ghahghahi , Edwin M. Fulcher , Aritharan Thurairajaratnam
发明人： Leah M. Miller , Farshad Ghahghahi , Edwin M. Fulcher , Aritharan Thurairajaratnam
IPC分类号： H01R909
CPC分类号： H05K1/0216 , H01R31/06 , H05K1/112 , H05K1/117 , H05K2201/09236 , H05K2201/09281 , H05K2201/09727
摘要： A structure for receiving electrical signals near a central portion of the structure and distributing the electrical signals to a peripheral portion of the structure. The structure has a first set of contacts arranged in an array near the central portion of the structure. Electrically conductive traces connect the first set of contacts to a second set of contacts, where each of the electrically conductive traces has at least a first segment, a second segment, and a third segment. The first segment of each of the electrically conductive traces has relatively narrow width and spacing. The first segment of each of the electrically conductive traces is connected on a first end of the first segment to one of the first set of contacts and on a second end of the first segment to the second segment of each of the electrically conductive traces. The second segment of each of the electrically conductive traces has relatively intermediate width and spacing. The second segment of each of the electrically conductive traces is connected on a first end of the second segment to the second end of the first segment and on a second end of the second segment to the third segment of each of the electrically conductive traces. The third segment of each of the electrically conductive traces has relatively wide width and spacing. The third segment of each of the electrically conductive traces is connected on a first end of the third segment to the second end of the second segment and on a second end of the third segment to one of the second set of contacts.
摘要翻译：一种用于在所述结构的中心部分附近接收电信号并将所述电信号分配到所述结构的外围部分的结构。该结构具有靠近结构的中心部分排列成阵列的第一组触点。导电迹线将第一组触点连接到第二组触点，其中每个导电迹线具有至少第一段，第二段和第三段。每个导电迹线的第一段具有相对较窄的宽度和间隔。每个导电迹线的第一段在第一段的第一端连接到第一组触点中的一个，并且在第一段的第二端连接到每个导电迹线的第二段。每个导电迹线的第二段具有相对中间的宽度和间隔。每个导电迹线的第二段在第二段的第一端连接到第一段的第二端，并且在第二段的第二端连接到每个导电迹线的第三段。每个导电迹线的第三段具有相对宽的宽度和间隔。每个导电迹线的第三段在第三段的第一端连接到第二段的第二端，并且在第三段的第二端连接到第二组接触中的一个。

6. 发明申请

US20060223341A1 Ball assignment system 有权
标题翻译：球分配系统
公开(公告)号：US20060223341A1
公开(公告)日：2006-10-05
申请号：US11097895
申请日：2005-04-01
申请人： Arun Ramakrishnan , Farshad Ghahghahi , Aritharan Thurairajaratnam , Leah Miller
发明人： Arun Ramakrishnan , Farshad Ghahghahi , Aritharan Thurairajaratnam , Leah Miller
IPC分类号： H05K1/00
CPC分类号： H01L23/49838 , H01L23/49816 , H01L23/66 , H01L2223/6638 , H01L2924/0002 , H01L2924/15311 , H05K1/112 , H05K2201/09227 , H05K2201/09236 , H05K2201/10734 , H01L2924/00
摘要： A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern. Substantially all of the contacts are disposed at a standard pitch one from another on a single contact surface.
摘要翻译：包括设置在图案的第一部分中的高速发射器触点的接触图案，其中高速发射器接触设置在发射机差分对中。高速接收器触点设置在图案的第二部分中，其中图案的第一部分不与图案的第二部分分散，并且高速接收器触点设置在接收器差分对中。在图案的第一部分和图案的第二部分之间设置至少一条其他触点的一条直线，其他触点不包含任何高速发送器触点和高速接收器触点。低速IO触点设置在图案的第三部分中，其中图案的第三部分相对于图案的第一部分和图案的第二部分布置在图案的内部。基本上所有的触点在单个接触表面上彼此之间以标准间距设置。

7. 发明授权

US07319272B2 Ball assignment system 有权
标题翻译：球分配系统
公开(公告)号：US07319272B2
公开(公告)日：2008-01-15
申请号：US11097895
申请日：2005-04-01
申请人： Arun Ramakrishnan , Farshad Ghahghahi , Aritharan Thurairajaratnam , Leah M. Miller
发明人： Arun Ramakrishnan , Farshad Ghahghahi , Aritharan Thurairajaratnam , Leah M. Miller
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/34
CPC分类号： H01L23/49838 , H01L23/49816 , H01L23/66 , H01L2223/6638 , H01L2924/0002 , H01L2924/15311 , H05K1/112 , H05K2201/09227 , H05K2201/09236 , H05K2201/10734 , H01L2924/00
摘要： A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern. Substantially all of the contacts are disposed at a standard pitch one from another on a single contact surface.
摘要翻译：包括设置在图案的第一部分中的高速发射器触点的接触图案，其中高速发射器接触设置在发射机差分对中。高速接收器触点设置在图案的第二部分中，其中图案的第一部分不与图案的第二部分分散，并且高速接收器触点设置在接收器差分对中。在图案的第一部分和图案的第二部分之间设置至少一条其他触点的一条直线，其他触点不包含任何高速发送器触点和高速接收器触点。低速IO触点设置在图案的第三部分中，其中图案的第三部分相对于图案的第一部分和图案的第二部分布置在图案的内部。基本上所有的触点在单个接触表面上彼此之间以标准间距设置。

8. 发明申请

US20050110167A1 Routing scheme for differential pairs in flip chip substrates 有权
标题翻译：倒装芯片基板差分对的布线方案
公开(公告)号：US20050110167A1
公开(公告)日：2005-05-26
申请号：US10720958
申请日：2003-11-24
申请人： Arun Ramakrishnan , Anand Govind , Farshad Ghahghahi
发明人： Arun Ramakrishnan , Anand Govind , Farshad Ghahghahi
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L23/49827 , H01L23/49838 , H01L2224/16 , H01L2224/73253 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011
摘要： A flip chip substrate is provided, which includes a plurality of conductive layers, including a top layer and a bottom layer. A first plurality of contacts, including first and second contacts corresponding to a differential signal pair, are arranged on the top layer within a die bonding area. A second plurality of contacts, including third and fourth contacts corresponding to the differential signal pair, are arranged on the bottom layer. First and second traces are routed between the first and third contacts and between the second and fourth contacts, respectively, wherein the second trace is routed out of the die bonding area on a different layer than the first trace. The traces are routed in a manner that reduces the length difference between the traces.
摘要翻译：提供了倒装芯片基板，其包括多个导电层，包括顶层和底层。包括对应于差分信号对的第一和第二触点的第一多个触点布置在芯片粘接区域内的顶层上。包括对应于差分信号对的第三和第四触点的第二多个触点布置在底层上。第一和第二迹线分别在第一和第三触点之间以及第二和第四触点之间布线，其中第二迹线在与第一迹线不同的层上被引导出芯片粘合区域外。迹线以减少迹线之间的长度差的方式布线。

9. 发明申请

US20050077081A1 Robust high density substrate design for thermal cycling reliability 有权
标题翻译：坚固的高密度基板设计，用于热循环可靠性
公开(公告)号：US20050077081A1
公开(公告)日：2005-04-14
申请号：US10681554
申请日：2003-10-08
申请人： Anand Govind , Zafer Kutlu , Farshad Ghahghahi
发明人： Anand Govind , Zafer Kutlu , Farshad Ghahghahi
IPC分类号： H01L23/498 , H05K1/11
CPC分类号： H01L23/49838 , H01L23/49816 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package for a die with improved thermal cycling reliability. A first layer of the package provides ball pads dispersed throughout. A second layer of the package provides signal traces. A high stress area associated with the corner of the dies is defined. Preferably the high stress area is defined as two ball pitches away from the corner of the die. Signal traces are routed away from the high stress area and in particular signal traces are routed away from the ball pads associated with the high stress to eliminate the cracks in the routed traces.
摘要翻译：一种具有改善热循环可靠性的模具的半导体封装。包装的第一层提供分散在其中的球垫。封装的第二层提供信号迹线。定义了与模具角部相关联的高应力区域。优选地，高应力区域被定义为远离模具角部的两个球距。信号迹线远离高应力区域，特别是信号迹线远离与高应力相关联的球垫，以消除路线迹线中的裂纹。

10. 发明授权

US07345245B2 Robust high density substrate design for thermal cycling reliability 有权
标题翻译：坚固的高密度基板设计，用于热循环可靠性
公开(公告)号：US07345245B2
公开(公告)日：2008-03-18
申请号：US10681554
申请日：2003-10-08
申请人： Anand Govind , Zafer Kutlu , Farshad Ghahghahi
发明人： Anand Govind , Zafer Kutlu , Farshad Ghahghahi
IPC分类号： H05K1/16
CPC分类号： H01L23/49838 , H01L23/49816 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package for a die with improved thermal cycling reliability. A first layer of the package provides ball pads dispersed throughout. A second layer of the package provides signal traces. A high stress area associated with the corner of the dies is defined. Preferably the high stress area is defined as two ball pitches away from the corner of the die. Signal traces are routed away from the high stress area and in particular signal traces are routed away from the ball pads associated with the high stress to eliminate the cracks in the routed traces.
摘要翻译：一种具有改善热循环可靠性的模具的半导体封装。包装的第一层提供分散在其中的球垫。封装的第二层提供信号迹线。定义了与模具角部相关联的高应力区域。优选地，高应力区域被定义为远离模具角部的两个球距。信号迹线远离高应力区域，特别是信号迹线远离与高应力相关的球垫，以消除路由迹线中的裂纹。

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