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1. 发明授权

US12052037B2 Enhancing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters 有权
公开(公告)号：US12052037B2
公开(公告)日：2024-07-30
申请号：US17702515
申请日：2022-03-23
申请人： Analog Devices, Inc.
发明人： Akira Shikata , Abhishek Bandyopadhyay
IPC分类号： H03M3/00
CPC分类号： H03M3/322 , H03M3/426
摘要： Systems and methods are provided for increasing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters. In some examples, systems and methods are provided for reducing total capacitance in an embedded excess loop delay compensation digital-to-analog converter (DAC) in a quantizer for a continuous time delta-sigma ADC. In other examples, the excess loop delay compensation DAC can be a current domain DAC, a charge domain DAC, or a voltage domain DAC. Additionally, methods are provided for digitally controlling the gain of an excess loop delay DAC. Furthermore, methods are provided to calibrate a gain mismatch between a main successive approximation register DAC and an excess loop delay DAC. The systems and methods provided herein improve performance of continuous time delta-sigma ADCs. Continuous time delta-sigma ADCs are high precision and power efficient ADCs, often used in audio playback devices and medical devices.

2. 发明授权

US09716470B2 Apparatus and methods for compensating an operational amplifier 有权
公开(公告)号：US09716470B2
公开(公告)日：2017-07-25
申请号：US14719221
申请日：2015-05-21
申请人： Analog Devices, Inc.
发明人： Abhishek Bandyopadhyay
IPC分类号： H03F1/02 , H03F3/45 , H03F3/30
CPC分类号： H03F1/0205 , H03F3/3022 , H03F3/45085 , H03F3/45183 , H03F3/45192 , H03F2203/45028 , H03F2203/45116 , H03F2203/45134 , H03F2203/45248
摘要： Provided herein are apparatus and methods for compensating an operational amplifier (op-amp). In certain configurations, a compensation network is electrically connected between an output node of the op-amp and an input differential pair coupled source/emitter tail-current node. The compensation network can include a capacitor having a relatively low value of capacitance. In this manner, op-amp bandwidth is improved while power consumption is reduced to meet a “green” standard.

3. 发明授权

US11539373B2 Method to compensate for metastability of asynchronous SAR within delta sigma modulator loop 有权
公开(公告)号：US11539373B2
公开(公告)日：2022-12-27
申请号：US17339369
申请日：2021-06-04
申请人： Analog Devices, Inc.
发明人： Abhishek Bandyopadhyay
IPC分类号： H03M1/34 , H03M1/46 , H03M1/08 , H03M1/12 , H03M3/00
摘要： Herein disclosed are some examples of metastability detectors and compensator circuitry for successive-approximation-register (SAR) analog-to-digital converters (ADCs) within delta sigma modulator (DSM) loops. A metastability detector may detect metastability at an output of a SAR ADC and compensator circuitry may implement a compensation scheme to compensate for the metastability. The identification of the metastability and/or compensation for the metastability can avoid detrimental effects and/or errors to the DSM loops that may be caused by the metastability of the SAR ADCS.

4. 发明授权

US11509327B2 System and method to enhance noise performance in a delta sigma converter 有权
公开(公告)号：US11509327B2
公开(公告)日：2022-11-22
申请号：US17396014
申请日：2021-08-06
申请人： Analog Devices, Inc.
发明人： Preston S. Birdsong , Abhishek Bandyopadhyay , Adam R. Spirer
IPC分类号： H03M7/32 , H03M7/36 , H03M3/00
摘要： Systems and methods for a power-efficient 3-level digital-to-analog converter. A converter cell using a current starving technique keeps a portion of the converter cell turned on in a low power mode, as opposed to completely turning off current in selected modes. A conversion system keeps a first set of converters active while allowing a second set of converters to be powered down. Systems and methods presented save power and allow for efficient reactivation of converters.

5. 发明授权

US09319004B2 Apparatus and methods for equalization 有权
标题翻译：用于均衡的装置和方法
公开(公告)号：US09319004B2
公开(公告)日：2016-04-19
申请号：US13684904
申请日：2012-11-26
申请人： ANALOG DEVICES, INC.
发明人： Abhishek Bandyopadhyay , David Paul Foley
IPC分类号： H03F1/34 , H03F3/45
CPC分类号： H03F1/34 , H03F3/45475 , H03F2203/45134 , H03F2203/45138 , H03F2203/45522 , H03F2203/45526
摘要： Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal.
摘要翻译：提供了用于均衡的装置和方法。在某些实现中，均衡器包括第一和第二反馈电阻器，第一和第二均衡电阻器，均衡电容器和包括第一至第四输入端子和第一和第二输出端子的放大电路。放大电路可以在第一和第三输入端子之间接收差分输入电压信号，并且第一和第二均衡电阻器和均衡电容器串联地电连接在第二和第四输入端子之间，均衡电容器在第一和第二输入端子之间均衡电阻。此外，第一反馈电阻器电连接在第一输出端子和第二输入端子之间，第二反馈电阻器电连接在第二输出端子和第四输入端子之间。

6. 发明授权

US12009791B2 Increasing power efficiency in a digital feedback class D driver 有权
公开(公告)号：US12009791B2
公开(公告)日：2024-06-11
申请号：US17702312
申请日：2022-03-23
申请人： Analog Devices, Inc.
发明人： Abhishek Bandyopadhyay
IPC分类号： H03F3/217 , H03M3/00 , H04R3/02
CPC分类号： H03F3/2175 , H03M3/412 , H03M3/464 , H04R3/02 , H03F2200/03 , H03F2200/331 , H03F2200/351
摘要： Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.

7. 发明授权

US11626885B1 Gain programmability techniques for delta-sigma analog-to-digital converter 有权
公开(公告)号：US11626885B1
公开(公告)日：2023-04-11
申请号：US17538187
申请日：2021-11-30
申请人： Analog Devices, Inc.
发明人： Shaolong Liu , Daniel Peter Canniff , Abhishek Bandyopadhyay , Akira Shikata
IPC分类号： H03M3/00 , H03M1/00 , H03M1/06 , H03M1/12
摘要： An excess loop delay compensation (ELDC) technique for use with a successive approximation register (SAR) based quantizer in a continuous time delta-sigma ADC is described. The techniques can efficiently program and calibrate the ELD gain in ELD compensation SAR quantizers. An ELDC circuit can include a charge pump having a digitally programmable capacitance to adjust a gain, such as the gain of the ELDC digital-to-analog converter (DAC) or the gain of the SAR DAC.

8. 发明授权

US11621722B2 Multi quantizer loops for delta-sigma converters 有权
公开(公告)号：US11621722B2
公开(公告)日：2023-04-04
申请号：US17459020
申请日：2021-08-27
申请人： Analog Devices, Inc.
发明人： Abhishek Bandyopadhyay , Akira Shikata
IPC分类号： H03M3/00
摘要： The number of bits in the quantizer can be decoupled from the number of bits in the feedback digital-to-analog converter (DAC) A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and a second quantizer coupled to an output of the first quantizer, where the second quantizer can receive the output of the first quantizer and generate an output having a second number of bits. The feedback DAC can be coupled to the second quantizer to receive a representation of the output of the second quantizer, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

9. 发明授权

US11757466B2 System and method for dynamic element matching for delta sigma converters 有权
公开(公告)号：US11757466B2
公开(公告)日：2023-09-12
申请号：US17395902
申请日：2021-08-06
申请人： Analog Devices, Inc.
发明人： Abhishek Bandyopadhyay , Preston S. Birdsong , Adam R. Spirer
IPC分类号： H03M1/66 , H03M3/00 , H04L25/03 , H04L25/49 , H03M1/74
CPC分类号： H03M3/50 , H03M1/66 , H03M3/39 , H04L25/03006 , H04L25/4917 , H03M1/747 , H04L2025/03363
摘要： Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other l-DACs. Techniques include decreasing mismatch among multiple l-DACs while improving efficiency of rotational dynamic element matching.

10. 发明申请

US20230060505A1 TECHNIQUES TO REDUCE QUANTIZATION NOISE IN DELTA SIGMA CONVERTERS 有权
公开(公告)号：US20230060505A1
公开(公告)日：2023-03-02
申请号：US17459071
申请日：2021-08-27
申请人： Analog Devices, Inc.
发明人： Abhishek Bandyopadhyay , Akira Shikata
IPC分类号： H03M3/00 , H03M1/08 , H03M1/68 , H03M1/46
摘要： This disclosure is directed to, among other things, techniques to decouple the number of bits in a quantizer from the number of bits in the feedback digital-to-analog converter (DAC). A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and then emulate a second quantizer, such as by using a bit truncation technique, to generate an output having a second number of bits. The feedback DAC can be coupled to receive the second number of bits, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

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