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1. 发明申请

US20090066399A1 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US20090066399A1
公开(公告)日：2009-03-12
申请号：US12230953
申请日：2008-09-09
申请人： An-Tung Chen , Li-Wen Fang , Hung-Der Su
发明人： An-Tung Chen , Li-Wen Fang , Hung-Der Su
IPC分类号： H03L5/00
CPC分类号： H03K3/012 , H03K3/35613
摘要： A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.
摘要翻译：电平移位电路包括通过两个节点彼此耦合的输入级和输出级。输入级根据输入信号改变节点上的电压，输出级根据两个节点上的电压来确定输出信号。在过渡状态下，输入级提供大电流以对第一节点或第二节点进行充电或放电，以便快速地改变其上的电压。在稳定状态下，输入级降低电流，从而降低功耗。

2. 发明授权

US07839197B2 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US07839197B2
公开(公告)日：2010-11-23
申请号：US12230953
申请日：2008-09-09
申请人： An-Tung Chen , Li-Wen Fang , Hung-Der Su
发明人： An-Tung Chen , Li-Wen Fang , Hung-Der Su
IPC分类号： H03L5/00
CPC分类号： H03K3/012 , H03K3/35613
摘要： A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.
摘要翻译：电平移位电路包括由两个节点彼此耦合的输入级和输出级。输入级根据输入信号改变节点上的电压，输出级根据两个节点上的电压来确定输出信号。在过渡状态下，输入级提供大电流以对第一节点或第二节点进行充电或放电，以便快速地改变其上的电压。在稳定状态下，输入级降低电流，从而降低功耗。

3. 发明授权

US07382172B2 Level shift circuit and method for the same 有权
标题翻译：电平移位电路及方法相同
公开(公告)号：US07382172B2
公开(公告)日：2008-06-03
申请号：US11497587
申请日：2006-08-02
申请人： Pao-Chuan Lin , Hung-Der Su , An-Tung Chen , Jing-Meng Liu
发明人： Pao-Chuan Lin , Hung-Der Su , An-Tung Chen , Jing-Meng Liu
IPC分类号： H03L5/00
CPC分类号： H03K3/35613 , H03K3/012
摘要： The present invention discloses a level shift circuit which comprises: level shift means for receiving an input of a first operational voltage and generating an output of a second operational voltage; and a current path connecting with a source of the second operational voltage and providing current to the output of the level shift means to speed up output level switching. The circuit preferably further comprises a power consumption control circuit for stopping excess power consumption when the output of the level shift means has substantially accomplished level switching.
摘要翻译：本发明公开了一种电平移位电路，包括：电平移位装置，用于接收第一工作电压的输入并产生第二工作电压的输出; 以及与第二工作电压源连接并将电流提供给电平移位装置的输出的电流路径，以加速输出电平切换。电路优选地还包括功率消耗控制电路，用于在电平移位装置的输出基本上实现电平切换时停止多余的功率消耗。

4. 发明授权

US07652536B2 Amplifier circuit with internal zeros 失效
标题翻译：具有内部零点的放大器电路
公开(公告)号：US07652536B2
公开(公告)日：2010-01-26
申请号：US12068774
申请日：2008-02-12
申请人： Hung-Der Su , Jing-Meng Liu , An-Tung Chen , Pao-Chuan Lin
发明人： Hung-Der Su , Jing-Meng Liu , An-Tung Chen , Pao-Chuan Lin
IPC分类号： H03F3/45 , H03F1/14
CPC分类号： H03F1/26 , H03F1/083 , H03F3/45197 , H03F2203/45356
摘要： An amplifier circuit with internal zeros provides a second pole in addition to a first pole and two zeros such that the second pole can prevent excessive gain at high frequency, so as to have high-frequency noise under control.
摘要翻译：具有内部零点的放大器电路除了第一极点和第二极点之外还提供第二极点，使得第二极点可以在高频下防止过高的增益，从而具有控制的高频噪声。

5. 发明申请

US20080211581A1 Amplifier circuit with internal zeros 失效
标题翻译：具有内部零点的放大器电路
公开(公告)号：US20080211581A1
公开(公告)日：2008-09-04
申请号：US12068774
申请日：2008-02-12
申请人： Hung-Der Su , Jing-Meng Liu , An-Tung Chen , Pao-Chuan Lin
发明人： Hung-Der Su , Jing-Meng Liu , An-Tung Chen , Pao-Chuan Lin
IPC分类号： H03F3/45
CPC分类号： H03F1/26 , H03F1/083 , H03F3/45197 , H03F2203/45356
摘要： An amplifier circuit with internal zeros provides a second pole in addition to a first pole and two zeros such that the second pole can prevent excessive gain at high frequency, so as to have high-frequency noise under control.
摘要翻译：具有内部零点的放大器电路除了第一极点和第二极点之外还提供第二极点，使得第二极点可以在高频下防止过高的增益，从而具有控制的高频噪声。

6. 发明申请

US20070290736A1 Level shift circuit and method for the same 有权
标题翻译：电平移位电路及方法相同
公开(公告)号：US20070290736A1
公开(公告)日：2007-12-20
申请号：US11497587
申请日：2006-08-02
申请人： Pao-Chuan Lin , Hung-Der Su , An-Tung Chen , Jing-Meng Liu
发明人： Pao-Chuan Lin , Hung-Der Su , An-Tung Chen , Jing-Meng Liu
IPC分类号： H03L5/00
CPC分类号： H03K3/35613 , H03K3/012
摘要： The present invention discloses a level shift circuit which comprises: level shift means for receiving an input of a first operational voltage and generating an output of a second operational voltage; and a current path connecting with a source of the second operational voltage and providing current to the output of the level shift means to speed up output level switching. The circuit preferably further comprises a power consumption control circuit for stopping excess power consumption when the output of the level shift means has substantially accomplished level switching.
摘要翻译：本发明公开了一种电平移位电路，包括：电平移位装置，用于接收第一工作电压的输入并产生第二工作电压的输出; 以及与第二工作电压源连接并将电流提供给电平移位装置的输出的电流路径，以加速输出电平切换。电路优选地还包括功率消耗控制电路，用于在电平移位装置的输出基本上实现电平切换时停止多余的功率消耗。

7. 发明授权

US08878304B2 Fuse circuit for final test trimming of integrated circuit chip 有权
标题翻译：保险丝电路，用于集成电路芯片的最终测试修整
公开(公告)号：US08878304B2
公开(公告)日：2014-11-04
申请号：US13358242
申请日：2012-01-25
申请人： Li-Wen Fang , Chih-Hao Yang , An-Tung Chen
发明人： Li-Wen Fang , Chih-Hao Yang , An-Tung Chen
IPC分类号： H01L27/06 , G11C29/00 , H01L27/02
CPC分类号： G11C29/785 , H01L27/0255 , H01L27/0617
摘要： The present invention discloses a fuse circuit for final test trimming of an integrated circuit (IC) chip. The fuse circuit includes at least one electrical fuse, at least one control switch corresponding to the electrical fuse, and a resistant device. The electrical fuse is connected with the control switch in series between a predetermined pin and a grounding pin. The control switch receives a control signal to determine whether a predetermined current flows through the corresponding electrical fuse and breaks the electrical fuse. The resistant device is coupled between a bulk terminal and a source terminal to increase a resistance of a parasitic channel, such that an electrostatic discharge (ESD) protection is enhanced, and errors of final test trimming of an IC chip are avoided.
摘要翻译：本发明公开了一种用于集成电路（IC）芯片的最终测试修整的熔丝电路。熔断器电路包括至少一个电熔丝，对应于电熔丝的至少一个控制开关和一个电阻装置。电保险丝与控制开关串联连接在预定的引脚和接地引脚之间。控制开关接收控制信号以确定预定电流是否流过相应的电熔丝并断开电熔丝。电阻器件耦合在体端子和源极端子之间以增加寄生沟道的电阻，从而增强了静电放电（ESD）保护，并且避免了IC芯片的最终测试修整的误差。

8. 发明申请

US20110018514A1 Dual-mode buck switching regulator and control circuit therefor 审中-公开
标题翻译：双模降压开关稳压器及其控制电路
公开(公告)号：US20110018514A1
公开(公告)日：2011-01-27
申请号：US12658692
申请日：2010-02-12
申请人： An-Tung Chen , Li-Wen Fang
发明人： An-Tung Chen , Li-Wen Fang
IPC分类号： G05F1/10
CPC分类号： H02M3/1588 , H02M2001/0032 , H02M2001/0048 , Y02B70/1466 , Y02B70/1491 , Y02B70/16
摘要： The present invention discloses a dual-mode buck switching regulator, comprising: a first power transistor having an end coupled to an input voltage and another end coupled to a common node; an inductor having an end coupled to the common node and another end coupled to the input voltage; a second power transistor having an end coupled to ground; a diode having an end coupled to ground; and a control circuit generating a first and a second switch control signals for controlling operations of the first and the second power transistors according to a feedback signal, and generating a mode selection signal according a mode control signal to select a synchronous or an asynchronous mode, wherein the second power transistor has another end which is coupled to the common node in the synchronous mode, and the diode has another end which is coupled to the common node in the asynchronous mode, and in the asynchronous mode: the another end of the second power transistor is not coupled to the common mode, or the second power transistor maintains off. The present invention also relates to a control circuit of the dual-mode buck switching regulator.
摘要翻译：本发明公开了一种双模降压开关调节器，包括：第一功率晶体管，其一端耦合到输入电压，另一端耦合到公共节点; 电感器，其端部耦合到公共节点，另一端耦合到输入电压; 第二功率晶体管，其端部耦合到地; 二极管，其一端与地耦合; 以及控制电路，根据反馈信号产生用于控制第一和第二功率晶体管的操作的第一和第二开关控制信号，并且根据模式控制信号产生模式选择信号以选择同步或异步模式，其中所述第二功率晶体管具有以同步模式耦合到所述公共节点的另一端，并且所述二极管具有以所述异步模式耦合到所述公共节点并且处于所述异步模式的另一端：所述第二功率晶体管的另一端功率晶体管不耦合到共模，或者第二功率晶体管保持断开。本发明还涉及双模降压开关调节器的控制电路。

9. 发明申请

US20130113049A1 FUSE CIRCUIT FOR FINAL TEST TRIMMING OF INTEGRATED CIRCUIT CHIP 有权
标题翻译：用于集成电路芯片最终测试的保险丝电路
公开(公告)号：US20130113049A1
公开(公告)日：2013-05-09
申请号：US13358242
申请日：2012-01-25
申请人： LI-WEN FANG , Chih-Hao Yang , An-Tung Chen
发明人： LI-WEN FANG , Chih-Hao Yang , An-Tung Chen
IPC分类号： H01L27/06
CPC分类号： G11C29/785 , H01L27/0255 , H01L27/0617
摘要： The present invention discloses a fuse circuit for final test trimming of an integrated circuit (IC) chip. The fuse circuit includes at least one electrical fuse, at least one control switch corresponding to the electrical fuse, and a resistant device. The electrical fuse is connected with the control switch in series between a predetermined pin and a grounding pin. The control switch receives a control signal to determine whether a predetermined current flows through the corresponding electrical fuse and breaks the electrical fuse. The resistant device is coupled between a bulk terminal and a source terminal to increase a resistance of a parasitic channel, such that an electrostatic discharge (ESD) protection is enhanced, and errors of final test trimming of an IC chip are avoided.
摘要翻译：本发明公开了一种用于集成电路（IC）芯片的最终测试修整的熔丝电路。熔断器电路包括至少一个电熔丝，对应于电熔丝的至少一个控制开关和一个电阻装置。电保险丝与控制开关串联连接在预定的引脚和接地引脚之间。控制开关接收控制信号以确定预定电流是否流过相应的电熔丝并断开电熔丝。电阻器件耦合在体端子和源极端子之间以增加寄生沟道的电阻，从而增强了静电放电（ESD）保护，并且避免了IC芯片的最终测试修整的误差。

10. 发明授权

US08451887B2 Phase interleaving control method for a multi-channel regulator system 有权
标题翻译：多通道调节器系统的相位交错控制方法
公开(公告)号：US08451887B2
公开(公告)日：2013-05-28
申请号：US13087466
申请日：2011-04-15
申请人： An-Tung Chen , Shao-Hung Lu , Isaac Y. Chen
发明人： An-Tung Chen , Shao-Hung Lu , Isaac Y. Chen
IPC分类号： H03K7/08
CPC分类号： H03K7/08 , H02M2003/1586 , H03K19/00346
摘要： A multi-channel regulator system includes serially connected PWM integrated circuits, each of which determines a PWM signal for a respective channel to operate therewith, and individually controls its operation mode according to whether or not an external clock is detected. Therefore, each channel will not be limited to operate under a constant mode and could become a master channel or a slave channel. Additionally, each of the PWM integrated circuits generates a phase shifted synchronous clock for its next channel during it is enabled, and thus all the channels operate in a synchronous but phase interleaving manner.
摘要翻译：多通道稳压器系统包括串联连接的PWM集成电路，每个PWM集成电路确定用于相应通道的PWM信号以进行操作，并且根据是否检测到外部时钟单独地控制其操作模式。因此，每个通道不限于在恒定模式下工作，并且可以成为主通道或从通道。此外，每个PWM集成电路在其使能期间产生用于其下一个通道的相移同步时钟，因此所有通道以同步但相位交错的方式工作。

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