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    • 1. 发明授权
    • Incremental placement during physical synthesis
    • 物理合成过程中的增量放置
    • US07536661B1
    • 2009-05-19
    • US11361370
    • 2006-02-24
    • Amit SinghKamal Chaudhary
    • Amit SinghKamal Chaudhary
    • G06F17/50
    • G06F17/5072
    • A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The critical region can be defined, at least in part, by at least one input block and at least one output block. Blocks of the critical region can be relocated to different sites within the critical region. The method further can include evaluating the relocation of blocks of the critical region according to a cost function and continuing to relocate blocks and evaluate the relocation of blocks in the critical region until at least one exit criterion is met.
    • 优化目标设备的电路设计的一部分的方法可以包括在电路设计的初始放置之后从多个区域识别关键区域。 关键区域可以至少部分地由至少一个输入块和至少一个输出块来定义。 关键区域的块可以重新定位到关键区域内的不同位置。 该方法还可以包括根据成本函数评估关键区域的块的重新定位,并且继续重新定位块并评估临界区域中块的重定位,直到满足至少一个退出准则。
    • 3. 发明授权
    • Pin reordering during placement of circuit designs
    • 电路设计放置期间引脚重新排序
    • US07058915B1
    • 2006-06-06
    • US10676445
    • 2003-09-30
    • Amit SinghKamal Chaudhary
    • Amit SinghKamal Chaudhary
    • G06F17/50
    • G06F17/5054G06F17/5072
    • A method (400) of placing a circuit design can include the steps of identifying topological levels of a circuit design representation (415) and determining an arrival time for each input signal to a look up table within a circuit design representation (420). The propagation delay associated with each pin of the look up table can be identified (420) such that the input signals of the look up table can be ordered according to the arrival times of each input signal and the propagation delay of each pin of the look up table (435). The method can continue processing each look up table of an identified topological level (440) as well as each topological level of the circuit design representation (455).
    • 放置电路设计的方法(400)可以包括以下步骤:确定电路设计表示的拓扑水平(415)并且确定每个输入信号到电路设计表示(420)内的查找表的到达时间。 可以识别与查找表的每个引脚相关联的传播延迟(420),使得可以根据每个输入信号的到达时间和查看表的每个引脚的传播延迟来排序查找表的输入信号 (435)。 该方法可以继续处理所识别的拓扑级别(440)的每个查找表以及电路设计表示的每个拓扑级别(455)。
    • 9. 发明授权
    • Methods and systems for defining a form navigational structure
    • 用于定义表单导航结构的方法和系统
    • US08347203B1
    • 2013-01-01
    • US11252566
    • 2005-10-19
    • Edy SetiawanAmit SinghFariborz Ebrahimi
    • Edy SetiawanAmit SinghFariborz Ebrahimi
    • G06F17/00
    • G06F17/3048G06F8/20
    • Systems and methods for defining a form navigational structure associated with at least one node in a process flow may comprise selecting a node form for the at least one node in the process flow, the node form identifying a plurality of displayable forms. Furthermore, the systems and methods may include defining a plurality of node steps for the node, each node step corresponding to a displayable screen associated with a subset of the plurality of displayable forms. Moreover, the systems and methods may include establishing a hierarchical tree structure associating the plurality of node steps, branches in the hierarchical tree structure having associated validation rules.
    • 用于定义与过程流程中的至少一个节点相关联的表单导航结构的系统和方法可以包括为进程流中的至少一个节点选择节点表单,该节点表单标识多个可显示形式。 此外,系统和方法可以包括为节点定义多个节点步骤,每个节点步骤对应于与多个可显示形式的子集相关联的可显示屏幕。 此外,系统和方法可以包括建立将多个节点步骤相关联的分层树结构,具有相关联的验证规则的分层树结构中的分支。