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1. 发明授权

US5537357A Method for preconditioning a nonvolatile memory array 失效
标题翻译：用于预处理非易失性存储器阵列的方法
公开(公告)号：US5537357A
公开(公告)日：1996-07-16
申请号：US266132
申请日：1994-06-27
申请人： Amit Merchant , Mickey L. Fandrich , Geoffrey Gould
发明人： Amit Merchant , Mickey L. Fandrich , Geoffrey Gould
IPC分类号： G11C16/10 , G11C16/34 , G11C7/02
CPC分类号： G11C16/107 , G11C16/10 , G11C16/3454 , G11C16/3459
摘要： A method of preconditioning a nonvolatile memory array including a first memory cell and a second memory cell. Preconditioning begins by applying an initial precondition pulse to all memory cells in the nonvolatile memory array without pausing to perform precondition verification. After this first step, precondition verification begins. The voltage level of the first memory cell is sensed and compared to a selected voltage level. If the threshold voltage of the first memory cell is below the selected voltage, the first memory cell did not precondition verify. In that case, another precondition pulse is then applied to the first memory cell. Application of precondition pulses and precondition verification continues until the first memory cell verifies as preconditioned. Attention turns to the second memory cell after the first memory cell precondition verifies. If the second memory cell does not precondition verify another precondition pulse is applied to the second memory cell. Application of precondition pulses and precondition verification continues until the second memory cell verifies as preconditioned.
摘要翻译：一种预处理包括第一存储单元和第二存储单元的非易失性存储器阵列的方法。通过向非易失性存储器阵列中的所有存储器单元应用初始预条件脉冲而不停止执行前提条件验证，开始预处理。在第一步之后，开始前提条件验证。感测第一存储器单元的电压电平并将其与选定的电压电平进行比较。如果第一存储单元的阈值电压低于所选择的电压，则第一存储单元未进行前提条件验证。在这种情况下，然后将另一个前提条件脉冲施加到第一存储器单元。预处理脉冲的应用和前提条件验证一直持续到第一个存储器单元验证为预处理。在第一个存储单元前提条件验证之后，注意转向第二个存储单元。如果第二存储器单元不是先决条件，则验证另一预条件脉冲被施加到第二存储器单元。预处理脉冲的应用和前提条件验证一直持续到第二个存储单元验证为预处理。

2. 发明授权

US5327383A Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy 失效
标题翻译：用于擦除结合行冗余的非易失性半导体存储器的方法和电路
公开(公告)号：US5327383A
公开(公告)日：1994-07-05
申请号：US871485
申请日：1992-04-21
申请人： Amit Merchant , Mickey L. Fandrich , Neal Mielke
发明人： Amit Merchant , Mickey L. Fandrich , Neal Mielke
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/16 , G11C29/00 , G11C29/04 , G11C7/00 , G11C7/02
CPC分类号： G11C29/82 , G11C16/10 , G11C16/16
摘要： Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control of erase events, the sequencer circuit allows easy modification of erase events. The sequencer circuit fires a precondition controller upon receipt of an erase command. The precondition controller then manages the preconditioning of the memory array, including memory cells within shorted rows. The precondition controller does so by disabling the replacement of shorted rows with redundant rows. During preconditioning each memory cell is programmed to a logic 0, before the memory cell is erased to a logic 1, to prevent the overerasure of memory cells during subsequent erasure. Afterward, the sequencer fires the erase controller. The erase control circuit then manages erasure. The circuitry also includes a postcondition controller and a program controller.
摘要翻译：描述用于独立地控制闪存的擦除的电路，包括用于替换存储器阵列内的短路行的冗余行。擦除命令将触发一个定序器电路，该电路对执行擦除事件任务的控制器进行调度。通过嵌套擦除事件的控制，定序器电路允许轻松修改擦除事件。定序器电路在接收到擦除命令时触发前提条件控制器。前置条件控制器然后管理存储器阵列的预处理，包括短路行内的存储器单元。前提条件控制器通过禁用用冗余行替换短路行来做到这一点。在预处理期间，在存储单元被擦除为逻辑1之前，每个存储器单元被编程为逻辑0，以防止在后续擦除期间存储器单元的过度擦写。之后，序列发生器触发擦除控制器。然后擦除控制电路管理擦除。电路还包括后置条件控制器和程序控制器。

3. 发明授权

US5377147A Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy 失效
标题翻译：用于预处理包含行冗余的非易失性半导体存储器中的短路行的方法和电路
公开(公告)号：US5377147A
公开(公告)日：1994-12-27
申请号：US105871
申请日：1993-08-11
申请人： Amit Merchant , Mickey L. Fandrich , Neal Mielke
发明人： Amit Merchant , Mickey L. Fandrich , Neal Mielke
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/34 , G11C29/00 , G11C29/04 , G11C11/40
CPC分类号： G11C29/82 , G11C16/3445 , G11C16/3468 , G11C16/3477
摘要： Circuitry for verifying the preconditioning of shorted cells within a flash memory cell. The preconditioning circuitry accommodates shorted cells, allowing them to pass verification at lower threshold voltage levels than good cells but ensuring the threshold voltage levels of shorted cells are high enough to prevent bitline leakage. The circuitry includes a sense amplifier for comparing the threshold voltage of a memory cell within the memory array to a selected reference threshold voltage level. The sense amplifier indicates whether the array memory cells exceeds the selected reference threshold voltage level. Selection circuitry couples two different reference cells to the sense amplifier, each having a different threshold voltage level. One of the reference cells has a normal threshold voltage level; i.e., a threshold voltage level to which good cells should be preconditioned. The other reference cell, a shorted reference cell, has a threshold voltage less than the nominal threshold voltage, but sufficient to prevent the quick overerasure of array cells during erasure. When the array cell is shorted to another cell within the array, selection circuitry selects the shorted reference cell. Otherwise, the other reference cell is selected.
摘要翻译：用于验证闪存单元内的短路单元的预处理的电路。预处理电路容纳短路单元，允许它们在比较好的单元更低的阈值电压电平下通过验证，但是确保短路单元的阈值电压电平足够高以防止位线泄漏。该电路包括读出放大器，用于将存储器阵列内的存储单元的阈值电压与选定的参考阈值电压电平进行比较。读出放大器指示阵列存储单元是否超过选定的参考阈值电压电平。选择电路将两个不同的参考单元耦合到读出放大器，每个具有不同的阈值电压电平。一个参考单元具有正常的阈值电压电平; 即要预处理好电池的阈值电压电平。另一个参考单元，短路参考单元，具有小于标称阈值电压的阈值电压，但足以防止在擦除期间阵列单元的快速过渡。当阵列单元与阵列内的另一单元短路时，选择电路选择短路参考单元。否则，选择另一个参考单元。

4. 发明授权

US5347489A Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy 失效
标题翻译：用于预处理包含行冗余的非易失性半导体存储器中的短路行的方法和电路
公开(公告)号：US5347489A
公开(公告)日：1994-09-13
申请号：US871848
申请日：1992-04-21
申请人： Amit Merchant , Mickey L. Fandrich , Neal Mielke
发明人： Amit Merchant , Mickey L. Fandrich , Neal Mielke
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/34 , G11C29/00 , G11C29/04 , G11C11/40
CPC分类号： G11C29/82 , G11C16/3445 , G11C16/3468 , G11C16/3477
摘要： A method of preconditioning and verifying the preconditioning of memory cells within shorted rows of a memory array is described. Preconditioning begins by applying a preconditioning pulse to two memory cells that are shorted together. Afterward, one of the two shorted cells is read by applying a nominal gate voltage level to the gates of both of the shorted memory cells. At the same time, a shorted reference cell is read by applying a voltage level to its gate which less than the nominal gate voltage level. While the read voltages are being applied to the array cells and the shorted reference cell, the threshold voltage of one of the two shorted array cells is compared to the threshold voltage of the shorted reference cell. The shorted reference cell has a threshold voltage level that is lower than the level normally required for preconditioning but which is sufficient to prevent the quick overerasure of the shorted memory cells.
摘要翻译：描述了一种对存储器阵列的短行内的存储单元进行预处理和验证预处理的方法。预处理开始于将预处理脉冲应用于短路在一起的两个存储单元。之后，通过对两个短路存储器单元的栅极施加标称栅极电压电平来读取两个短路单元之一。同时，通过向其栅极施加小于额定栅极电压电平的电压电平来读取短路参考电池。当读取电压被施加到阵列单元和短路参考单元时，将两个短路阵列单元之一的阈值电压与短路参考单元的阈值电压进行比较。短路参考电池具有低于预处理通常所需的电平的阈值电压电平，但足以防止短路存储器单元的快速过热。

5. 发明授权

US5623620A Special test modes for a page buffer shared resource in a memory device 失效
标题翻译：存储设备中页面缓冲区共享资源的特殊测试模式
公开(公告)号：US5623620A
公开(公告)日：1997-04-22
申请号：US85542
申请日：1993-06-30
申请人： Mickey L. Fandrich , Salim B. Fedel , Ranjeet Alexis , Mamun Rashid
发明人： Mickey L. Fandrich , Salim B. Fedel , Ranjeet Alexis , Mamun Rashid
IPC分类号： G01R31/3185 , G06F11/22 , G06F12/02 , G11C11/00 , G11C16/10 , G11C29/26 , G11C29/48
CPC分类号： G11C29/48 , G01R31/318516 , G06F12/0246 , G11C11/005 , G11C16/10 , G11C29/26 , G06F11/2273 , G06F2212/7203
摘要： A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
摘要翻译：一种具有特殊测试模式的页面缓冲电路的闪存设备。页面缓冲电路包括平面A和平面B，每个平面包括静态随机存取存储器阵列。页面缓冲电路还包括模式控制电路，其将平面A和平面B映射为可通过主机总线访问的连续扩展存储器空间。页面缓冲电路还将平面A和平面B映射为闪存器件的闪存阵列控制器的控制存储器。

6. 发明授权

US5546561A Circuitry and method for selectively protecting the integrity of data stored within a range of addresses within a non-volatile semiconductor memory 失效
标题翻译：用于选择性地保护存储在非易失性半导体存储器内的地址范围内的数据的完整性的电路和方法
公开(公告)号：US5546561A
公开(公告)日：1996-08-13
申请号：US372891
申请日：1995-01-13
申请人： Virgil N. Kynett , Mickey L. Fandrich
发明人： Virgil N. Kynett , Mickey L. Fandrich
IPC分类号： G11C16/10 , G11C16/34 , G06F12/14 , G11C7/00
CPC分类号： G11C16/3445 , G11C16/102 , G11C16/3436 , G11C16/3459
摘要： A circuit for selectively protecting data stored within a range of addresses from programming and erasing. The circuit includes a circuit for generating an active lock signal. The circuit generates an active lock signal when a protect signal is active and an address signal represents an address within the protected range. Both erasure and programming are prevented while the lock signal is active. Programming and erasure of protected data is permitted while the lock signal is inactive. A method for selectively protecting data within a range of addresses on a non-volatile semiconductor memory from programming or erasure is also described.
摘要翻译：用于选择性地保护存储在地址范围内的数据不被编程和擦除的电路。该电路包括用于产生主动锁定信号的电路。当保护信号有效并且地址信号表示受保护范围内的地址时，该电路产生有效的锁定信号。当锁定信号有效时，可以防止擦除和编程。当锁定信号无效时，允许对受保护数据进行编程和擦除。还描述了一种用于选择性地保护非易失性半导体存储器上的地址范围内的数据不被编程或擦除的方法。

7. 发明授权

US5430677A Architecture for reading information from a memory array 失效
标题翻译：从内存数组读取信息的架构
公开(公告)号：US5430677A
公开(公告)日：1995-07-04
申请号：US239939
申请日：1994-05-09
申请人： Mickey L. Fandrich , Owen Jungroth
发明人： Mickey L. Fandrich , Owen Jungroth
IPC分类号： G11C16/28 , G11C29/40 , G11C29/48 , G11C7/00
CPC分类号： G11C29/40 , G11C16/28 , G11C29/48
摘要： In a memory array having a plurality of rows and columns of memory devices for storing binary conditions, apparatus for selecting particular memory devices, a sense amplifier for transferring indications of the conditions of selected memory devices, and apparatus for generating signals indicative of conditions other than the state of the memory devices, the improvement including a multiplexor, the multiplexor being arranged to accept as input the output of the sense amplifier and the signals indicative of conditions other than the state of the memory devices, the multiplexor and the apparatus for generating signals indicative of conditions other than the state of the memory devices being positioned in a manner that parasitic capacitance affecting the input to the sense amplifier is not created. The output of the sense amplifier may also be connected to other internal circuits so that the memory array may be accessed while bringing other signals to the output pins.
摘要翻译：在具有用于存储二进制条件的存储器装置的多个行和列的存储器阵列中，用于选择特定存储器件的装置，用于传送所选择的存储器件的条件的指示的读出放大器，以及用于产生指示除了所述存储器件的状态，所述改进包括多路复用器，所述多路复用器被布置为接受所述读出放大器的输出作为输入，以及指示所述存储器件状态以外的条件的信号，所述多路复用器和用于产生信号的装置指示除了存储器件的状态之外的条件，其方式是不产生影响读出放大器的输入的寄生电容。读出放大器的输出也可以连接到其他内部电路，使得可以访问存储器阵列，同时向输出引脚提供其他信号。

8. 发明授权

US5412793A Method for testing erase characteristics of a flash memory array 失效
标题翻译：测试闪存阵列擦除特性的方法
公开(公告)号：US5412793A
公开(公告)日：1995-05-02
申请号：US277369
申请日：1994-07-19
申请人： Jerry Kreifels , Mickey L. Fandrich , William Smith
发明人： Jerry Kreifels , Mickey L. Fandrich , William Smith
IPC分类号： G11C16/16 , G11C29/20 , G11C29/34 , G11C29/46 , G11C29/50 , G06F12/00
CPC分类号： G11C29/34 , G11C16/16 , G11C29/20 , G11C29/46 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2216/20
摘要： A method of determining erasure characteristics of a nonvolatile semiconductor memory array using an on-board write state machine is described. The method begins by configuring the write state machine to apply a single erase pulse to the array and then issuing an erase command. If array erasure is unsuccessful, another erase command is issued. Erase commands are reissued until every address within the array is successfully erased.
摘要翻译：描述使用板上写入状态机确定非易失性半导体存储器阵列的擦除特性的方法。该方法从配置写状态机开始，将单个擦除脉冲施加到阵列，然后发出擦除命令。如果阵列擦除不成功，则会发出另一个擦除命令。擦除命令将重新发布，直到阵列中的每个地址成功擦除为止。

9. 发明授权

US5369754A Block specific status information in a memory device 失效
公开(公告)号：US5369754A
公开(公告)日：1994-11-29
申请号：US220811
申请日：1994-03-30
申请人： Mickey L. Fandrich , Chakravarthy Yarlagadda , Rodney R. Rozman , Geoffrey A. Gould
发明人： Mickey L. Fandrich , Chakravarthy Yarlagadda , Rodney R. Rozman , Geoffrey A. Gould
IPC分类号： G06F12/14 , G11C7/24 , G11C16/10 , G11C16/22 , G06F12/00
CPC分类号： G06F12/1425 , G11C16/102 , G11C16/22 , G11C7/24 , G06F2212/2022
摘要： A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.

10. 发明授权

US5353256A Block specific status information in a memory device 失效
标题翻译：阻止存储设备中的特定状态信息
公开(公告)号：US5353256A
公开(公告)日：1994-10-04
申请号：US85293
申请日：1993-06-30
申请人： Mickey L. Fandrich , Chakravarthy Yarlagadda , Rodney R. Rozman , Geoffrey A. Gould
发明人： Mickey L. Fandrich , Chakravarthy Yarlagadda , Rodney R. Rozman , Geoffrey A. Gould
IPC分类号： G06F12/14 , G11C7/24 , G11C16/10 , G11C16/22 , G11C7/00
CPC分类号： G06F12/1425 , G11C16/102 , G11C16/22 , G11C7/24 , G06F2212/2022
摘要： A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.
摘要翻译：具有多个闪存阵列块的闪速存储器件和包含用于存储每个闪存阵列块的块状态的块状态寄存器的块状态寄存器电路。闪存器件中的闪存阵列控制器电路对闪存阵列块执行编程或擦除操作，并在每个块状态寄存器中保持块状态。闪速存储器件中的接口电路使得能够通过总线对块状态寄存器进行读取访问。

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