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1. 发明授权

US5490279A Method and apparatus for operating a single CPU computer system as a multiprocessor system 失效
标题翻译：将单CPU计算机系统作为多处理器系统运行的方法和装置
公开(公告)号：US5490279A
公开(公告)日：1996-02-06
申请号：US065597
申请日：1993-05-21
申请人： Adalberto Golbert , Douglas M. Carean , Roshan J. Fernando , Amar A. Ghori , Yoav Hochberg , Robert F. Krick , Milind Mittal , Anurag Sah
发明人： Adalberto Golbert , Douglas M. Carean , Roshan J. Fernando , Amar A. Ghori , Yoav Hochberg , Robert F. Krick , Milind Mittal , Anurag Sah
IPC分类号： G06F15/177 , G06F9/38 , G06F13/40 , G06F15/167 , G06F3/00 , G06F15/17
CPC分类号： G06F9/3879 , G06F13/4068 , G06F15/167
摘要： A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.
摘要翻译：一种仅通过插入第二微处理器集成电路将单处理器系统升级到多处理系统的方法和装置。计算机系统具有用于接收第二处理单元的升级插座，以及升级插座和现有处理器之间的专用通信总线，用于处理处理器间通信，总线仲裁和高速缓存一致性等。第二处理器对系统来说是透明的，该系统保持其内存管理单元和缓存系统以及其他安排，就像它仍然是一个单处理系统一样。因此，提供了一种便宜的方法和装置，用于大大提高单处理系统与多处理系统的速度，而无需传统上与多处理系统相关联的成本。

2. 发明授权

US5884091A Computer system having a central processing unit responsive to the identity of an upgrade processor 失效
标题翻译：具有响应于升级处理器的身份的中央处理单元的计算机系统
公开(公告)号：US5884091A
公开(公告)日：1999-03-16
申请号：US248376
申请日：1994-05-24
申请人： Amar A. Ghori , Adalberto Golbert , Robert F. Krick
发明人： Amar A. Ghori , Adalberto Golbert , Robert F. Krick
IPC分类号： G06F13/14 , G06F9/38 , G06F9/445 , G06F13/38 , G06F15/177 , G06F15/00
CPC分类号： G06F15/177 , G06F9/3877 , G06F9/3879 , G06F9/4403 , G06F9/4405
摘要： A uniprocessing computer system is provided with an original CPU and an upgrade socket for receiving an additional processor that need not be of a single predetermined type. On system RESET, the original CPU determines if an upgrade processor is resident in the upgrade socket and, if so, what kind of upgrade processor is present. Each upgrade processor is equipped with a programmed data word for identifying the upgrade type and its features. The system includes a mechanism for communicating this upgrade information from the upgrade processor to the original CPU. The processors cooperatively configure the system properly according to the identity and features of the upgrade processor.
摘要翻译：一个单一处理计算机系统提供有一个原始CPU和一个升级套接字，用于接收不需要一个预定类型的附加处理器。在系统复位时，原始CPU确定升级处理器是否驻留在升级套接字中，如果是，则显示什么样的升级处理器。每个升级处理器配备有编程数据字，用于识别升级类型及其功能。该系统包括用于将升级信息从升级处理器传送到原始CPU的机制。处理器根据升级处理器的身份和特征协调配置系统。

3. 发明授权

US5355467A Second level cache controller unit and system 失效
标题翻译：二级缓存控制器单元和系统
公开(公告)号：US5355467A
公开(公告)日：1994-10-11
申请号：US208090
申请日：1994-03-08
申请人： Peter D. MacWilliams , Robert L. Farrell , Adalberto Golbert , Itzik Silas
发明人： Peter D. MacWilliams , Robert L. Farrell , Adalberto Golbert , Itzik Silas
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F2212/6082
摘要： A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.
摘要翻译：实现为集成电路单元的第二级高速缓冲存储器控制器与辅助随机存取高速缓冲存储器和主存储器（系统）总线控制器一起操作以形成第二级高速缓存存储器子系统。该子系统与本地处理器（CPU）总线和主存储器总线接口，由总线提供独立的访问，从而当CPU所需的数据位于二级缓存中时，减少主存储器总线的流量。类似地，当主存储器总线的二级缓存访问被窃听并回写到主存储器时，CPU总线流量被最小化。与主存储器总线连接的监听锁存器通过次级高速缓存控制器单元中的高速缓存目录提供对高速缓冲存储器的窥探访问。控制器还支持使用最近使用（MRU）主存储器直写和流水线存储器总线周期请求的控制器标签阵列和二级缓存中的并行查找。

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