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1. 发明授权

US09501092B1 Systems and methods for clock alignment using pipeline stages 有权
标题翻译：使用流水线阶段进行时钟对准的系统和方法
公开(公告)号：US09501092B1
公开(公告)日：2016-11-22
申请号：US14974506
申请日：2015-12-18
申请人： Altera Corporation
发明人： Dana How , Carl Ebeling , Audrey Catherine Kertesz
IPC分类号： H03L7/06 , G06F1/12
CPC分类号： H04L7/02 , G06F1/12 , H04L7/0054
摘要： Systems and methods for phase detection are disclosed. A collapsible three-stage pipeline includes a first register in a first stage having a first clock signal having first clock edges, a second register in a second stage that receives a first signal from the first stage, and having a second clock signal having second clock edges, and a third register in a third stage that receives a second signal from the second stage, and having a third clock signal having third clock edges, wherein each second clock edge has a corresponding first clock edge and a corresponding third clock edge. The circuitry may further include a two-stage pipeline including fourth and fifth stages, a counter that provides an input signal into the collapsible three-stage pipeline and the two-stage pipeline, and a comparator that compares a first output of the collapsible three-stage pipeline and a second output of the two-stage pipeline.
摘要翻译：公开了用于相位检测的系统和方法。可折叠三级流水线包括第一级中的第一寄存器，其具有具有第一时钟沿的第一时钟信号，第二级中的第二寄存器，其接收来自第一级的第一信号，并具有第二时钟信号，该第二时钟信号具有第二时钟边缘和第三寄存器，其接收来自第二级的第二信号，并具有具有第三时钟沿的第三时钟信号，其中每个第二时钟沿具有对应的第一时钟沿和对应的第三时钟沿。该电路还可以包括一个包括第四和第五级的两级流水线，一个向可折叠的三级流水线和两级流水线提供输入信号的计数器，以及比较器，阶段管道和二级管道的第二输出。

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