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1. 发明授权

US07865747B2 Adaptive issue queue for reduced power at high performance 有权
标题翻译：自适应问题队列，在高性能下降低功耗
公开(公告)号：US07865747B2
公开(公告)日：2011-01-04
申请号：US09971186
申请日：2001-10-05
申请人： Alper Buyuktosunoglu , Stanley E. Schuster , David M. Brooks , Pradip Bose , Peter W. Cook , David H. Albonesi
发明人： Alper Buyuktosunoglu , Stanley E. Schuster , David M. Brooks , Pradip Bose , Peter W. Cook , David H. Albonesi
IPC分类号： G06F1/32
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/329 , G06F9/3802 , G06F9/3814 , Y02D10/24
摘要： A method and structure of reducing power consumption in a microprocessor includes at least one storage structure in which the activity of the storage structure is dynamically measured and the size of the structure is controlled based on the activity. The storage structure includes a plurality of blocks, and the size of the structure is controlled in units of block size, based on activity measured in the blocks. An exemplary embodiment is an adaptive out-of-order queue.
摘要翻译：降低微处理器功耗的方法和结构包括至少一个存储结构，其中动态地测量存储结构的活动，并且基于活动来控制结构的大小。存储结构包括多个块，并且基于块中测量的活动，以块大小为单位来控制结构的大小。示例性实施例是自适应失序队列。

2. 发明授权

US07134028B2 Processor with low overhead predictive supply voltage gating for leakage power reduction 有权
标题翻译：具有低开销预测电源电压门控的处理器，用于泄漏功率降低
公开(公告)号：US07134028B2
公开(公告)日：2006-11-07
申请号：US10428170
申请日：2003-05-01
申请人： Pradip Bose , David M. Brooks , Peter W. Cook , Philip G. Emma , Michael K. Gschwind , Stanley E. Schuster , Vijayalakshmi Srinivasan
发明人： Pradip Bose , David M. Brooks , Peter W. Cook , Philip G. Emma , Michael K. Gschwind , Stanley E. Schuster , Vijayalakshmi Srinivasan
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F9/3869 , G06F1/3203 , G06F1/3243 , G06F1/3246 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： An integrated circuit (IC) including unit power control, leakage reduction circuit for controllably reducing leakage power with reduced LdI/dt noise in the IC and, an activity prediction unit invoking active/dormant states in IC units. The prediction unit determines turn on and turn off times for each IC unit. The prediction unit controls a supply voltage select circuit selectively passing a supply voltage to a separate supply line at the predicted turn on time and selectively blocking the supply voltage at the predicted turn off time.
摘要翻译：包括单元功率控制的集成电路（IC），用于可控地减少IC中的LdI / dt噪声的泄漏功率的泄漏降低电路，以及在IC单元中调用主动/休眠状态的活动预测单元。预测单元确定每个IC单元的导通和关闭时间。预测单元控制电源电压选择电路，其在预测的导通时间选择性地将电源电压传递到单独的电源线，并且在预测的关断时间选择性地阻断电源电压。

3. 发明授权

US07065665B2 Interlocked synchronous pipeline clock gating 有权
公开(公告)号：US07065665B2
公开(公告)日：2006-06-20
申请号：US10262769
申请日：2002-10-02
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： H04L5/00 , G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

4. 发明授权

US07308593B2 Interlocked synchronous pipeline clock gating 有权
标题翻译：联锁同步管道时钟门控
公开(公告)号：US07308593B2
公开(公告)日：2007-12-11
申请号：US11376544
申请日：2006-03-14
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： H04L5/00 , G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译：一种包括管道的集成电路和操作管道的方法。流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

5. 发明授权

US07685457B2 Interlocked synchronous pipeline clock gating 失效
标题翻译：联锁同步管道时钟门控
公开(公告)号：US07685457B2
公开(公告)日：2010-03-23
申请号：US11846847
申请日：2007-08-29
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译：一种包括管道的集成电路和操作管道的方法。流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

6. 发明授权

US07475227B2 Method of stalling one or more stages in an interlocked synchronous pipeline 有权
标题翻译：在联锁同步管道中停止一个或多个阶段的方法
公开(公告)号：US07475227B2
公开(公告)日：2009-01-06
申请号：US11375989
申请日：2006-03-14
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： G06F9/30 , H04L5/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： A method of operating an integrated circuit including a pipeline and a method of stalling stages in the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译：一种操作包括流水线的集成电路的方法和在管线中停止级的方法。流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

7. 发明授权

US07076681B2 Processor with demand-driven clock throttling power reduction 失效
标题翻译：处理器采用需求驱动的时钟节流功率降低
公开(公告)号：US07076681B2
公开(公告)日：2006-07-11
申请号：US10187698
申请日：2002-07-02
申请人： Pradip Bose , Daniel M. Citron , Peter W. Cook , Philip G. Emma , Hans M. Jacobson , Prabhakar N. Kudva , Stanley E. Schuster , Jude A. Rivers , Victor V. Zyuban
发明人： Pradip Bose , Daniel M. Citron , Peter W. Cook , Philip G. Emma , Hans M. Jacobson , Prabhakar N. Kudva , Stanley E. Schuster , Jude A. Rivers , Victor V. Zyuban
IPC分类号： G06F1/04
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3802 , G06F9/3836 , G06F9/384 , G06F9/3867 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.
摘要翻译：同步集成电路，如标量处理器或超标量处理器。电路组件或单元由公共系统时钟计时并同步。至少两个时钟单元包括多个寄存器级，例如流水线级。每个时钟单元中的本地时钟发生器将来自一个或多个其他单元的公共系统时钟和失速状态相结合，以调整寄存器时钟频率向上或向下。

8. 发明授权

US06829716B2 Latch structure for interlocked pipelined CMOS (IPCMOS) circuits 失效
标题翻译：用于联锁流水线CMOS（IPCMOS）电路的锁存结构
公开(公告)号：US06829716B2
公开(公告)日：2004-12-07
申请号：US09836375
申请日：2001-04-17
申请人： Peter W. Cook , Stanley E. Schuster
发明人： Peter W. Cook , Stanley E. Schuster
IPC分类号： G06F104
CPC分类号： G06F7/00 , G06F9/3869 , G06F9/3871
摘要： Circuits and methods for operating a latch structure are disclosed. The circuits include a plurality of stages, and each stage includes a first logic circuit, a latch coupled to a second logic circuit of an adjacent stage and a switch which connects the first logic circuit to the latch in a first state and disconnects the logic circuit from the latch in a second state. A local clock circuit controls the first and second states by providing a locally generated clock signal to activate the switch. The locally generated clock signals are generated by interlocking handshake signals from a local clock circuit of an adjacent stage.
摘要翻译：公开了用于操作闩锁结构的电路和方法。电路包括多个级，并且每个级包括第一逻辑电路，耦合到相邻级的第二逻辑电路的锁存器和在第一状态下将第一逻辑电路连接到锁存器的开关，并且断开逻辑电路从第二状态的锁存器。本地时钟电路通过提供本地生成的时钟信号来激活开关来控制第一和第二状态。本地生成的时钟信号通过来自相邻级的本地时钟电路的互锁信号产生。

9. 发明授权

US4199695A Avoidance of hot electron operation of voltage stressed bootstrap drivers 失效
标题翻译：避免电压应力引导驱动器的热电子操作
公开(公告)号：US4199695A
公开(公告)日：1980-04-22
申请号：US883429
申请日：1978-03-03
申请人： Peter W. Cook , Stanley E. Schuster
发明人： Peter W. Cook , Stanley E. Schuster
IPC分类号： H01L27/04 , G06F1/04 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L29/78 , H03K5/02 , H03K17/082 , H03K19/003 , H03K19/017 , H03K3/353
CPC分类号： H03K5/023 , G06F1/04 , H01L27/06 , H01L29/78 , H03K17/0822 , H03K19/00315 , H03K19/01714
摘要： An improved field effect transistor circuit adapted to operate at high switching speeds and to avoid hot electron operation of voltage stressed FET bootstrap drivers. The circuit comprises a voltage control means adapted to maintain a simultaneous gate and drain to source voltage of FET devices within a characteristic hot electron operational voltage range. The voltage control means is adapted to reduce FET drain to source voltage by connecting a plurality of FET devices in series to reduce the drain to source voltage drop across each device. The drain to source voltage is further defined by connecting the common nodes of successive series connected devices to a specified voltage source that is less than a characteristic hot electron drain to source voltage. The voltage control means also includes a gate voltage clamping FET that is adapted to hold down the gate of a device when the drain to source voltage of the device rises above a particular hot electron voltage. The voltage control means further comprises a plurality of timing pulses that define particular combinations of gate and drain to source device voltages that are less than characteristic combined hot electron voltages. The voltage control means further includes devices with width to length ratios adapted to provide close voltage tracking between input drain voltages and output source voltages to maintain a minimum drain to source voltage drop. The operation of the hot electron voltage control means is particularly described with respect to embodiments using voltage stressed bootstrap driver FETs to generate on chip clock phases.
摘要翻译：一种改进的场效应晶体管电路，适于在高开关速度下工作并避免受压应力FET自举驱动器的热电子操作。该电路包括电压控制装置，其适于在特征热电子工作电压范围内保持FET器件的同时栅极和漏极到源极电压。电压控制装置适于通过串联连接多个FET器件来减少FET漏极到源极电压，以减少跨越每个器件的漏极到源极电压降。通过将连续串联连接的器件的公共节点连接到小于特征热电子漏极到源极电压的指定电压源，进一步限定漏极到源极电压。电压控制装置还包括栅极电压钳位FET，其适于在器件的漏极 - 源极电压升高到特定热电子电压之上时压住器件的栅极。电压控制装置还包括多个定时脉冲，其限定小于特征组合热电子电压的栅极和漏极与源极器件电压的特定组合。电压控制装置还包括宽度与长度比适合于在输入漏极电压和输出源电压之间提供紧密电压跟踪的装置，以保持对源极电压降的最小漏极。关于使用电压应力自举驱动器FET以产生片上时钟相位的实施例，特别描述了热电子电压控制装置的操作。

10. 发明授权

US06848060B2 Synchronous to asynchronous to synchronous interface 失效
标题翻译：同步异步到同步接口
公开(公告)号：US06848060B2
公开(公告)日：2005-01-25
申请号：US09794467
申请日：2001-02-27
申请人： Peter W. Cook , Stanley E. Schuster
发明人： Peter W. Cook , Stanley E. Schuster
IPC分类号： G06F13/42 , G06F9/38 , G06F3/00
CPC分类号： G06F9/3869 , G06F9/3871
摘要： An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.
摘要翻译：同步和异步数据传输之间的接口包括彼此耦合以形成用于数据传输的流水线的多个级。多级包括执行与异步数据传送同步的第一级，至异步数据传输异步的至少一个中间级和执行异步到同步数据传输的最后级。同步时钟路径在多个级上传播定时信号，以便当定时信号存在于该级时使第一级和最后级能够执行操作。

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