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1. 发明授权

US5477168A Finite state machine with means for the reduction of noise effects 失效
标题翻译：有限状态机具有降低噪音效果的手段
公开(公告)号：US5477168A
公开(公告)日：1995-12-19
申请号：US219060
申请日：1994-03-29
申请人： Aloysius P. Thijssen , Franciscus G. M. Bouwman , Hendrik A. Vink
发明人： Aloysius P. Thijssen , Franciscus G. M. Bouwman , Hendrik A. Vink
IPC分类号： G05B9/02 , G06F7/00 , H03K19/173
CPC分类号： G06F7/00
摘要： A finite state machine that may receive actuator signals and has a plurality of elementary sequential logic elements fed by the actuator signals. Through various interconnections between the elements a first set of interconnected logic states is realized that are activated through combined occurrence of a particular predecessor state and an associated actuator signal. In various ones of said logic states a particular output signal is produced. Furthermore, the finite state machine has a subset of redundant logic states that are aggregated together with a particular operational by appropriate interconnections for collectively emulating the operational state in question.
摘要翻译：可以接收致动器信号并具有由致动器信号馈送的多个基本顺序逻辑元件的有限状态机。通过元件之间的各种互连，实现了通过特定前驱状态和相关联的致动器信号的组合发生而被激活的第一组互连的逻辑状态。在各种逻辑状态中，产生特定的输出信号。此外，有限状态机具有通过适当互连聚合在一起的特定操作的冗余逻辑状态的子集，以共同模拟所讨论的操作状态。

2. 发明授权

US5325367A Memory device containing a static ram memory that is adapted for executing a self-test, and integrated circuit containing such a device as an embedded static ram memory 失效
标题翻译：包含用于执行自检的静态RAM存储器的存储器件以及包含诸如嵌入式静态RAM的这种设备的集成电路
公开(公告)号：US5325367A
公开(公告)日：1994-06-28
申请号：US752166
申请日：1991-08-22
申请人： Robertus W. C. Dekker , Aloysius P. Thijssen , Franciscus P. M. Beenker , Joris F. P. Jansen
发明人： Robertus W. C. Dekker , Aloysius P. Thijssen , Franciscus P. M. Beenker , Joris F. P. Jansen
IPC分类号： G11C29/00 , G06F11/22 , G11C11/401 , G11C29/12 , G11C29/20 , G11C29/40
CPC分类号： G11C29/20 , G11C29/40
摘要： A memory device that contains a static RAM memory is provided with data input and data output registers, an address register, and a control register for storing various control signals. The RAM has three principal modes:a. in a normal mode, all registers are accessible externally so that the memory may fulfill its standard function,b. in a scan-state, all the cited register constitute a synchronous shift register that may be serially written with a test pattern and serially read with a result pattern; in this way the memory may be subjected to a test according to the scan test principle,c. in a self test state the communication with the outer world is shut off, the address register counts through successive addresses, the memory is cycled through read-modify or read-modify-read operations, and the data read is conversed to a signature pattern for subsequent scan-out. In this way a quasi stand-alone test facility is realized. Various additional features may be implemented.
摘要翻译：包含静态RAM存储器的存储器件提供有数据输入和数据输出寄存器，地址寄存器和用于存储各种控制信号的控制寄存器。 RAM有三种主要模式：a。在正常模式下，所有寄存器可从外部访问，以便存储器可以完成其标准功能，b。在扫描状态下，所有引用的寄存器构成同步移位寄存器，其可以用测试图形串行写入并且以结果模式串行读取; 以这种方式，存储器可以根据扫描测试原理进行测试，c。在自检状态下，与外部世界的通信被关闭，地址寄存器通过连续地址计数，存储器通过读取修改或读取 - 修改 - 读取操作循环，并且读取的数据被转换为签名模式随后扫描。以这种方式实现了一个准独立的测试设施。可以实现各种附加特征。

3. 发明授权

US5911064A Clock multiplexer with selection and deselection of clock modules 失效
标题翻译：时钟复用器，选择和取消选择时钟模块
公开(公告)号：US5911064A
公开(公告)日：1999-06-08
申请号：US988711
申请日：1997-12-11
申请人： Sebastianus M. Samsom , Aloysius P. Thijssen , Keith Baker
发明人： Sebastianus M. Samsom , Aloysius P. Thijssen , Keith Baker
IPC分类号： H03K5/00 , G06F1/06 , H03K17/00
CPC分类号： H03K17/002 , G06F1/04
摘要： A circuit includes a plurality of logically identical clock modules which are all capable of driving the same clock output. The circuit has a selection input for selecting one of the clock modules for driving the clock output. After a change of the selection, a clock module just deselected awaits the completion of a period of the own clock signal before switching to deselection. The clock modules have a hold-off input which is coupled to a common signal line. A newly selected clock module switches to a selection state only after a beginning of a period of the own clock signal, provided that the selected clock module previously detects a signal on its hold-off input which indicates that all clock modules have deselected themselves. The common signal line is preferably coupled to the clock output, deselection being detected on the basis of the signal level which occurs after the beginning of the period after a change of the selection.
摘要翻译：电路包括多个逻辑上相同的时钟模块，它们都能够驱动相同的时钟输出。电路具有用于选择用于驱动时钟输出的时钟模块之一的选择输入。在更改选择之后，刚刚取消选择的时钟模块等待完成自己的时钟信号的一段时间，然后再切换到取消选择。时钟模块具有耦合到公共信号线的保持输入。新选择的时钟模块仅在自己的时钟信号的周期的开始之后切换到选择状态，前提是所选择的时钟模块先前在其保持输入端检测到指示所有时钟模块已被取消选择的信号。公共信号线优选地耦合到时钟输出，基于在选择改变之后的周期开始之后发生的信号电平来检测取消选择。

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