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1. 发明申请

US20110197049A1 TWO PASS TEST CASE GENERATION USING SELF-MODIFYING INSTRUCTION REPLACEMENT 失效
标题翻译：使用自我修改指示替换的两次测试案例生成
公开(公告)号：US20110197049A1
公开(公告)日：2011-08-11
申请号：US12700970
申请日：2010-02-05
申请人： Allon Adir , Brad Lee Herold , John Martin Ludden , Pedro Martin-de-Nicolas , Charles Leverett Meissner , Gil Eliezer Shurek
发明人： Allon Adir , Brad Lee Herold , John Martin Ludden , Pedro Martin-de-Nicolas , Charles Leverett Meissner , Gil Eliezer Shurek
IPC分类号： G06F9/38
CPC分类号： G06F9/3816 , G06F9/3005
摘要： A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the redirection instruction with a replacement instruction having a desired result resolved in accordance with the current machine state. The instructions that are replaced may be conditional branch instructions and the result a desired execution path. The examination of the machine state permits determination of a branch condition for the replacement instruction so that the next pass of the test code executes along the desired path. Alternatively, the handler can execute a jump to the branch instruction, causing immediate execution of the desired branch path. The re-direction instructions may be illegal instructions, which cause execution of an interrupt handler that performs the replacement.
摘要翻译：使用特殊重定向指令替代具有机器状态相关结果的指令的测试代码生成技术提供测试代码的生成，其中在不使用状态模型的情况下进行状态相关的执行选择。重定向指令导致处理程序的执行，而不是检查机器状态，并根据当前机器状态用具有期望结果的替换指令替换重定向指令。被替换的指令可以是条件分支指令，并且结果是可能的执行路径。对机器状态的检查允许确定替换指令的分支条件，使得测试代码的下一遍沿着期望的路径执行。或者，处理程序可以执行跳转到分支指令，导致立即执行所需的分支路径。重定向指令可能是非法指令，这些指令导致执行替换的中断处理程序的执行。

2. 发明授权

US08516229B2 Two pass test case generation using self-modifying instruction replacement 失效
标题翻译：双通测试用例生成使用自修改指令替换
公开(公告)号：US08516229B2
公开(公告)日：2013-08-20
申请号：US12700970
申请日：2010-02-05
申请人： Allon Adir , Brad Lee Herold , John Martin Ludden , Pedro Martin-de-Nicolas , Charles Leverett Meissner , Gil Eliezer Shurek
发明人： Allon Adir , Brad Lee Herold , John Martin Ludden , Pedro Martin-de-Nicolas , Charles Leverett Meissner , Gil Eliezer Shurek
IPC分类号： G06F9/44
CPC分类号： G06F9/3816 , G06F9/3005
摘要： A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the redirection instruction with a replacement instruction having a desired result resolved in accordance with the current machine state. The instructions that are replaced may be conditional branch instructions and the result a desired execution path. The examination of the machine state permits determination of a branch condition for the replacement instruction so that the next pass of the test code executes along the desired path. Alternatively, the handler can execute a jump to the branch instruction, causing immediate execution of the desired branch path. The re-direction instructions may be illegal instructions, which cause execution of an interrupt handler that performs the replacement.
摘要翻译：使用特殊重定向指令替代具有机器状态相关结果的指令的测试代码生成技术提供测试代码的生成，其中在不使用状态模型的情况下进行状态相关的执行选择。重定向指令导致处理程序的执行，而不是检查机器状态，并根据当前机器状态用具有期望结果的替换指令替换重定向指令。被替换的指令可以是条件分支指令，并且结果是可能的执行路径。对机器状态的检查允许确定替换指令的分支条件，使得测试代码的下一遍沿着期望的路径执行。或者，处理程序可以执行跳转到分支指令，导致立即执行所需的分支路径。重定向指令可能是非法指令，这些指令导致执行替换的中断处理程序的执行。

3. 发明授权

US07945888B2 Model-based hardware exerciser, device, system and method thereof 有权
标题翻译：基于模型的硬件训练器，设备，系统及其方法
公开(公告)号：US07945888B2
公开(公告)日：2011-05-17
申请号：US12038818
申请日：2008-02-28
申请人： Allon Adir , Gil Eliezer Shurek
发明人： Allon Adir , Gil Eliezer Shurek
IPC分类号： G06F17/50 , G06F9/44 , G06F9/455 , G06F11/22
CPC分类号： G06F11/261 , G06F17/5022
摘要： Device, system and method for verification of a hardware system-under-test including at least one processor. A method includes building an executable image of a hardware exerciser adapted for execution on a test platform selected from: a simulation accelerator, a hardware emulator, a prototype hardware system, and a hardware production wafer. The exerciser image includes embedded data corresponding to architectural knowledge, testing knowledge, and a test template. The test template is defined in a context-free formal language and includes biasing directives to influence at least one of a desired test structure, one or more resources to be included in the test, and one or more values of the included resources. The architectural knowledge is obtained from an architectural model including a formal description of the specification for the system-under-test, and the testing knowledge is obtained from a testing knowledgebase including heuristics for testing desired aspects of the system-under-test.
摘要翻译：用于验证包括至少一个处理器的被测硬件系统的设备，系统和方法。一种方法包括构建适于在选自以下的测试平台上执行的硬件训练器的可执行映像：模拟加速器，硬件仿真器，原型硬件系统和硬件生产晶片。训练者图像包括对应于建筑知识，测试知识和测试模板的嵌入数据。测试模板以无上下文的形式语言定义，并且包括偏好指令以影响期望的测试结构，要包括在测试中的一个或多个资源中的至少一个以及所包括的资源的一个或多个值。建筑知识是从建筑模型中获得的，包括对被测系统的规范的正式描述，并且测试知识从测试知识库获得，包括用于测试被测系统的期望方面的启发式。

4. 发明申请

US20090222694A1 Model-Based Hardware Exerciser, Device, System and Method Thereof 有权
标题翻译：基于模型的硬件练习器，设备，系统及方法
公开(公告)号：US20090222694A1
公开(公告)日：2009-09-03
申请号：US12038818
申请日：2008-02-28
申请人： Allon Adir , Gil Eliezer Shurek
发明人： Allon Adir , Gil Eliezer Shurek
IPC分类号： G06F11/00
CPC分类号： G06F11/261 , G06F17/5022
摘要： Device, system and method for verification of a hardware system-under-test including at least one processor. A method includes building an executable image of a hardware exerciser adapted for execution on a test platform selected from: a simulation accelerator, a hardware emulator, a prototype hardware system, and a hardware production wafer. The exerciser image includes embedded data corresponding to architectural knowledge, testing knowledge, and a test template. The test template is defined in a context-free formal language and includes biasing directives to influence at least one of a desired test structure, one or more resources to be included in the test, and one or more values of the included resources. The architectural knowledge is obtained from an architectural model including a formal description of the specification for the system-under-test, and the testing knowledge is obtained from a testing knowledgebase including heuristics for testing desired aspects of the system-under-test.
摘要翻译：用于验证包括至少一个处理器的被测硬件系统的设备，系统和方法。一种方法包括构建适于在选自以下的测试平台上执行的硬件训练器的可执行映像：模拟加速器，硬件仿真器，原型硬件系统和硬件生产晶片。训练者图像包括对应于建筑知识，测试知识和测试模板的嵌入数据。测试模板以无上下文的形式语言定义，并且包括偏好指令以影响期望的测试结构，要包括在测试中的一个或多个资源中的至少一个以及所包括的资源的一个或多个值。建筑知识是从建筑模型中获得的，包括对被测系统的规范的正式描述，并且测试知识从测试知识库获得，包括用于测试待测系统的期望方面的启发式。

5. 发明申请

US20080208827A1 Device, System and Method of Modeling Homogeneous Information 失效
标题翻译：设备，系统和均匀信息建模方法
公开(公告)号：US20080208827A1
公开(公告)日：2008-08-28
申请号：US11677589
申请日：2007-02-22
申请人： Allon Adir , Roy Emek , Eitan Marcus , Gil Eliezer Shurek
发明人： Allon Adir , Roy Emek , Eitan Marcus , Gil Eliezer Shurek
IPC分类号： G06F17/30
CPC分类号： G06F17/30604
摘要： Device, system and method of modeling homogeneous information. For example, a method that includes providing to a model-based application an input model including a refinable homogeneous record having a base type, wherein said homogeneous record is defined with a homogeneous constraint to only include data members of a type compatible with the base type. The homogeneous record is defined in a modeling environment that is able to automatically enforce the homogeneous constraint for the homogeneous record and for refinements thereof.
摘要翻译：设备，系统和均匀信息建模方法。例如，一种方法，其包括向基于模型的应用提供包括具有基本类型的可修改同构记录的输入模型，其中所述同构记录被定义为具有均匀约束，以仅包括与基本类型兼容的类型的数据成员。在建模环境中定义了同质记录，该建模环境能够自动强制同构记录的均匀约束及其优化。

6. 发明授权

US08458652B2 Device, system and method of modeling homogeneous information 失效
标题翻译：设备，系统和均匀信息建模方法
公开(公告)号：US08458652B2
公开(公告)日：2013-06-04
申请号：US11677589
申请日：2007-02-22
申请人： Allon Adir , Roy Emek , Eitan Marcus , Gil Eliezer Shurek
发明人： Allon Adir , Roy Emek , Eitan Marcus , Gil Eliezer Shurek
IPC分类号： G06F9/44
CPC分类号： G06F17/30604
摘要： Device, system and method of modeling homogeneous information. For example, a method that includes providing to a model-based application an input model including a refinable homogeneous record having a base type, wherein said homogeneous record is defined with a homogeneous constraint to only include data members of a type compatible with the base type. The homogeneous record is defined in a modeling environment that is able to automatically enforce the homogeneous constraint for the homogeneous record and for refinements thereof.
摘要翻译：设备，系统和均匀信息建模方法。例如，一种方法，其包括向基于模型的应用提供包括具有基本类型的可修改同构记录的输入模型，其中所述同构记录被定义为具有均匀约束，以仅包括与基本类型兼容的类型的数据成员。在建模环境中定义了同质记录，该建模环境能够自动强制同构记录的均匀约束及其优化。

7. 发明申请

US20120054560A1 VERIFYING CORRECTNESS OF PROCESSOR TRANSACTIONS 失效
标题翻译：验证加工商交易的正确性
公开(公告)号：US20120054560A1
公开(公告)日：2012-03-01
申请号：US12843068
申请日：2010-08-26
申请人： Allon Adir , John Martin Ludden , Avi Ziv
发明人： Allon Adir , John Martin Ludden , Avi Ziv
IPC分类号： G06F11/00 , G06F9/45
CPC分类号： G06F17/5022 , G06F11/3664 , G06F2217/68
摘要： An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.
摘要翻译：通过模拟测试程序的执行和更新交易顺序图以识别周期来检查处理器相对于交易的操作。基于在第一事务的执行期间读取的值和被配置为设置具有读取值的存储器的第二事务来更新该图。该测试程序包括用于识别第二个事务的信息。

8. 发明授权

US08589734B2 Verifying correctness of processor transactions 失效
标题翻译：验证处理器事务的正确性
公开(公告)号：US08589734B2
公开(公告)日：2013-11-19
申请号：US12843068
申请日：2010-08-26
申请人： Allon Adir , John Martin Ludden , Avi Ziv
发明人： Allon Adir , John Martin Ludden , Avi Ziv
IPC分类号： G06F11/00
CPC分类号： G06F17/5022 , G06F11/3664 , G06F2217/68
摘要： An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.
摘要翻译：通过模拟测试程序的执行和更新交易顺序图以识别周期来检查处理器相对于交易的操作。基于在第一事务的执行期间读取的值和被配置为设置具有读取值的存储器的第二事务来更新该图。该测试程序包括用于识别第二个事务的信息。

9. 发明申请

US20110208945A1 GENERATING RANDOM ADDRESSES FOR VERIFICATION OF DISTRIBUTED COMPUTERIZED DEVICES 失效
标题翻译：生成用于验证分布式计算机设备的随机地址
公开(公告)号：US20110208945A1
公开(公告)日：2011-08-25
申请号：US12709533
申请日：2010-02-22
申请人： Allon Adir , Gil Shurek
发明人： Allon Adir , Gil Shurek
IPC分类号： G06F12/00
CPC分类号： G06F12/1425
摘要： Testing a circuit in a post-silicon stage is performed by enabling the different processing entities of the circuit to determine a consistent access permissions schema in a random manner. Based upon the consistent access permissions schema, addresses to be accessed during the testing of the circuit may be determined. The addresses may be determined in a random manner. The consistent permissions schema may be determined based on a template representative of repetitive portions of access permissions schema. The disclosed subject matter may utilize biasing modules to bias the test generation to provide a test having a predetermined characteristic. The disclosed subject matter may utilize a joint random seed or other techniques to provide for consistent random decisions by the different processing entities.
摘要翻译：通过使电路的不同处理实体以随机方式确定一致的访问许可模式来执行后硅阶段中的电路测试。基于一致的访问许可模式，可以确定在电路测试期间要访问的地址。地址可以以随机方式确定。可以基于表示访问许可模式的重复部分的模板来确定一致的权限模式。所公开的主题可以利用偏置模块来偏置测试生成以提供具有预定特性的测试。所公开的主题可以利用联合随机种子或其他技术来提供不同处理实体的一致随机决定。

10. 发明授权

US06925405B2 Adaptive test program generation 失效
标题翻译：自适应测试程序生成
公开(公告)号：US06925405B2
公开(公告)日：2005-08-02
申请号：US10040940
申请日：2002-01-09
申请人： Allon Adir , Roy Emek , Eitan Marcus
发明人： Allon Adir , Roy Emek , Eitan Marcus
IPC分类号： G01R27/28 , G06F11/263 , G06F19/00
CPC分类号： G06F11/263
摘要： A test program generator that produces test instructions according to a specification of a system being verified. The instructions are typically generated randomly, at least in part, and are then. The system is capable of interpreting events, detecting an impending occurrence of an event, and responding to the event by switching to an alternate input stream.
摘要翻译：一种测试程序生成器，其根据被验证的系统的规范产生测试指令。指令通常随机生成，至少部分地，然后是。该系统能够解释事件，检测即将发生的事件，以及通过切换到替代输入流来响应事件。

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