专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07870430B2 Method and apparatus for sharing debug resources 有权
标题翻译：共享调试资源的方法和装置
公开(公告)号：US07870430B2
公开(公告)日：2011-01-11
申请号：US12040215
申请日：2008-02-29
申请人： Alistair P. Robertson , William C. Moyer , Ray C. Marshall
发明人： Alistair P. Robertson , William C. Moyer , Ray C. Marshall
IPC分类号： G06F11/00
CPC分类号： G06F11/3648 , G06F11/2236
摘要： A method includes providing an integrated circuit having a plurality of debug resources. The debug resources are usable exclusively for debug operations. The debug operations include operations directed by debug software executed by the integrated circuit and operations directed by external debug hardware which is external to the integrated circuit. The method further includes enabling availability of a first portion of the debug resources for use by the debug software, where a second portion of the debug resources are committed for exclusive use by the external debug hardware. The first portion is exclusive of the second portion. The method includes performing operations directed by the debug software using at least one debug resource of the first portion of the debug resources and operations directed by the external debug hardware using at least one debug resource of the second portion of the debug resources.
摘要翻译：一种方法包括提供具有多个调试资源的集成电路。调试资源专用于调试操作。调试操作包括由集成电路执行的调试软件和由集成电路外部的外部调试硬件引导的操作所执行的操作。该方法还包括使得调试资源的第一部分的可用性被调试软件使用，其中调试资源的第二部分被提交供外部调试硬件专用。第一部分不包括第二部分。该方法包括使用调试资源的第一部分的至少一个调试资源和外部调试硬件使用调试资源的第二部分的至少一个调试资源来执行的操作来执行由调试软件执行的操作。

2. 发明申请

US20090222692A1 METHOD AND APPARATUS FOR SHARING DEBUG RESOURCES 有权
标题翻译：用于共享调试资源的方法和装置
公开(公告)号：US20090222692A1
公开(公告)日：2009-09-03
申请号：US12040215
申请日：2008-02-29
申请人： Alistair P. Robertson , William C. Moyer , Ray C. Marshall
发明人： Alistair P. Robertson , William C. Moyer , Ray C. Marshall
IPC分类号： G06F11/22
CPC分类号： G06F11/3648 , G06F11/2236
摘要： A method includes providing an integrated circuit having a plurality of debug resources. The debug resources are usable exclusively for debug operations. The debug operations include operations directed by debug software executed by the integrated circuit and operations directed by external debug hardware which is external to the integrated circuit. The method further includes enabling availability of a first portion of the debug resources for use by the debug software, where a second portion of the debug resources are committed for exclusive use by the external debug hardware. The first portion is exclusive of the second portion. The method includes performing operations directed by the debug software using at least one debug resource of the first portion of the debug resources and operations directed by the external debug hardware using at least one debug resource of the second portion of the debug resources.
摘要翻译：一种方法包括提供具有多个调试资源的集成电路。调试资源专用于调试操作。调试操作包括由集成电路执行的调试软件和由集成电路外部的外部调试硬件引导的操作所执行的操作。该方法还包括使得调试资源的第一部分的可用性被调试软件使用，其中调试资源的第二部分被提交供外部调试硬件专用。第一部分不包括第二部分。该方法包括使用调试资源的第一部分的至少一个调试资源和外部调试硬件使用调试资源的第二部分的至少一个调试资源来执行的操作来执行由调试软件执行的操作。

3. 发明授权

US07447867B2 Non-intrusive address mapping having a modified address space identifier and circuitry therefor 有权
标题翻译：非侵入式地址映射具有修改的地址空间标识符及其电路
公开(公告)号：US07447867B2
公开(公告)日：2008-11-04
申请号：US11413430
申请日：2006-04-28
申请人： Richard Soja , William C. Moyer , Ray C. Marshall
发明人： Richard Soja , William C. Moyer , Ray C. Marshall
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0292
摘要： A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one external signal generated outside the processor, using the effective address and the modified address space identifier to form a logical address, and providing a physical address corresponding to the logical address. When the effective address has a first effective address value, the address space identifier has a first address space identifier value, and the mapping modifier has a first mapping value, the physical address has a first physical address value. When the effective address has the first effective address value, the address space identifier has the first address space identifier value, and the mapping modifier has a second mapping value, the physical address has a second physical address value.
摘要翻译：一种方法包括提供有效地址，提供标识当前执行过程的地址空间标识符，提供映射修饰符以形成修改的地址空间标识符，其中映射修饰符基于在处理器外部生成的至少一个外部信号，使用有效地址和修改的地址空间标识符以形成逻辑地址，并提供对应于逻辑地址的物理地址。当有效地址具有第一有效地址值时，地址空间标识符具有第一地址空间标识符值，并且映射修饰符具有第一映射值，物理地址具有第一物理地址值。当有效地址具有第一有效地址值时，地址空间标识符具有第一地址空间标识符值，并且映射修饰符具有第二映射值，物理地址具有第二物理地址值。

4. 发明授权

US07401201B2 Processor and method for altering address translation 有权
标题翻译：用于改变地址转换的处理器和方法
公开(公告)号：US07401201B2
公开(公告)日：2008-07-15
申请号：US11413422
申请日：2006-04-28
申请人： William C. Moyer , Ray C. Marshall , Richard Soja
发明人： William C. Moyer , Ray C. Marshall , Richard Soja
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.
摘要翻译：在具有地址转换表的处理器中，一种方法包括提供逻辑地址和控制信号。当控制信号具有第一值时，对应于逻辑地址提供第一物理地址，并且当控制信号具有第二值时，提供第二物理地址。第一物理地址和第二物理地址存储在地址转换表的至少一个有效条目中。在一种情况下，第一物理地址存储在具有与逻辑地址匹配的标签字段的第一有效条目中，并且第二物理地址被存储在具有与逻辑地址匹配的标签字段的第二有效条目中。或者，第一物理地址存储在第一有效条目的第一字段中，并且第二物理地址存储在第一有效条目的第二字段中。

5. 发明授权

US09552279B2 Data bus network interface module and method therefor 有权
标题翻译：数据总线网络接口模块及其方法
公开(公告)号：US09552279B2
公开(公告)日：2017-01-24
申请号：US13968591
申请日：2013-08-16
申请人： Mark Maiolani , Ray C. Marshall , Gary L. Miller
发明人： Mark Maiolani , Ray C. Marshall , Gary L. Miller
IPC分类号： G06F11/36
CPC分类号： G06F11/3656
摘要： A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.
摘要翻译：描述了一种数据总线网络接口模块，用于经由数据总线网络使得能够从集成数字信号处理设备的至少一个主机处理模块接收和传送应用消息。所述数据总线网络接口模块被布置成经由所述数据总线网络从至少一个远程网络节点接收至少一个数据总线消息，读取所接收的至少一个数据总线消息的标识符字段，并且使所接收的数据总线消息的数据内容如果标识符字段包括为调试使用定义的标识符值，则至少一个数据总线消息可用于至少一个调试模块。

6. 发明授权

US09292372B2 Error pad for safety device 有权
标题翻译：安全装置的错误垫
公开(公告)号：US09292372B2
公开(公告)日：2016-03-22
申请号：US14280652
申请日：2014-05-18
申请人： Chandan Gupta , Neha Bagri , Ray C. Marshall
发明人： Chandan Gupta , Neha Bagri , Ray C. Marshall
IPC分类号： G06F11/00 , G06F11/07 , G06F17/50 , H03K19/173
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/0751 , G06F17/5045 , H03K19/1737
摘要： A safety device with an error indication function includes at least one ERROR pad configured between the error indication function and at least one normal function, and a set of multiplexers connected to the ERROR pad. The safety device further includes an error indication block and a functional block multiplexed by the set of multiplexers. The error indication block includes a fault collection and control unit for collecting and providing error occurrence information to the ERROR pad, and an ERROR pad select control register for storing ERROR pad selection and configuration information to control select inputs of the first set of multiplexers and provide the ERROR pad configuration information to the ERROR pad.
摘要翻译：具有错误指示功能的安全装置包括在错误指示功能和至少一个正常功能之间配置的至少一个错误焊盘以及连接到ERROR焊盘的一组多路复用器。安全装置还包括错误指示块和由多路复用器组复用的功能块。错误指示块包括故障收集和控制单元，用于收集并提供错误发生信息给ERROR焊盘;以及错误焊盘选择控制寄存器，用于存储ERROR焊盘选择和配置信息，以控制第一组多路复用器的选择输入，并提供将ERROR焊盘配置信息提供给ERROR焊盘。

7. 发明申请

US20150052405A1 DATA BUS NETWORK INTERFACE MODULE AND METHOD THEREFOR 有权
标题翻译：数据总线网络接口模块及其方法
公开(公告)号：US20150052405A1
公开(公告)日：2015-02-19
申请号：US13968591
申请日：2013-08-16
申请人： Mark Maiolani , Ray C. Marshall , Gary L. Miller
发明人： Mark Maiolani , Ray C. Marshall , Gary L. Miller
IPC分类号： G06F11/34
CPC分类号： G06F11/3656
摘要： A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.
摘要翻译：描述了一种数据总线网络接口模块，用于经由数据总线网络使得能够从集成数字信号处理设备的至少一个主机处理模块接收和传送应用消息。所述数据总线网络接口模块被布置成经由所述数据总线网络从至少一个远程网络节点接收至少一个数据总线消息，读取所接收的至少一个数据总线消息的标识符字段，并且使所接收的数据总线消息的数据内容如果标识符字段包括为调试使用定义的标识符值，则至少一个数据总线消息可用于至少一个调试模块。

8. 发明申请

US20150331740A1 ERROR PAD FOR SAFETY DEVICE 有权
标题翻译：用于安全装置的错误垫
公开(公告)号：US20150331740A1
公开(公告)日：2015-11-19
申请号：US14280652
申请日：2014-05-18
申请人： Chandan Gupta , Neha Bagri , Ray C. Marshall
发明人： Chandan Gupta , Neha Bagri , Ray C. Marshall
IPC分类号： G06F11/07
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/0751 , G06F17/5045 , H03K19/1737
摘要： A safety device with an error indication function includes at least one ERROR pad configured between the error indication function and at least one normal function, and a set of multiplexers connected to the ERROR pad. The safety device further includes an error indication block and a functional block multiplexed by the set of multiplexers. The error indication block includes a fault collection and control unit for collecting and providing error occurrence information to the ERROR pad, and an ERROR pad select control register for storing ERROR pad selection and configuration information to control select inputs of the first set of multiplexers and provide the ERROR pad configuration information to the ERROR pad.
摘要翻译：具有错误指示功能的安全装置包括在错误指示功能和至少一个正常功能之间配置的至少一个错误焊盘以及连接到ERROR焊盘的一组多路复用器。安全装置还包括错误指示块和由多路复用器组复用的功能块。错误指示块包括故障收集和控制单元，用于收集并提供错误发生信息给ERROR焊盘;以及错误焊盘选择控制寄存器，用于存储ERROR焊盘选择和配置信息，以控制第一组多路复用器的选择输入，并提供将ERROR焊盘配置信息提供给ERROR焊盘。

9. 发明授权

US08954773B2 Electronic device and method for controlling current of a processor load by slewing clock frequency 有权
标题翻译：用于通过回转时钟频率控制处理器负载电流的电子设备和方法
公开(公告)号：US08954773B2
公开(公告)日：2015-02-10
申请号：US12091034
申请日：2005-10-21
申请人： Jenifer M. Scott , Michael R. Garrard , Ray C. Marshall
发明人： Jenifer M. Scott , Michael R. Garrard , Ray C. Marshall
IPC分类号： G06F1/26 , H03L7/08 , G06F1/08 , H03L7/197
CPC分类号： G06F1/08 , G06F1/26 , G06F2203/014 , H03L7/0802 , H03L7/197 , H03L7/1974
摘要： An electronic device comprises a voltage regulator supplying a current to a load such as a micro-controller unit. The load controls the current provided to the load from the voltage regulator. Preferably, the load controls the level of current supplied to the load upon start-up, thereby avoiding power surges being drawn by the load.
摘要翻译：电子设备包括向诸如微控制器单元之类的负载提供电流的电压调节器。负载控制从电压调节器提供给负载的电流。优选地，负载控制启动时提供给负载的电流电平，从而避免由负载引起的电涌。

10. 发明授权

US08615610B2 Interface system and method with backward compatibility 有权
标题翻译：接口系统和方法具有向后兼容性
公开(公告)号：US08615610B2
公开(公告)日：2013-12-24
申请号：US13248348
申请日：2011-09-29
申请人： Gary L. Miller , Ray C. Marshall , Jehoda Refaeli
发明人： Gary L. Miller , Ray C. Marshall , Jehoda Refaeli
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/4072 , G01R31/318533 , H04L25/0272
摘要： An interface including first and second transport protocol circuitry, a memory and a mode controller. The interface includes first and second physical interface types which are both selectively enabled to interface a set of pads. The first transport protocol circuitry is operative with the first type physical interface in a first mode and the second transport protocol circuitry is operative with the second type physical interface in a second mode. The memory stores a mode value indicative of the operating mode. The mode controller enables one of the physical interface types and a corresponding transport protocol based on the mode value. The first mode is the default mode, and the mode controller enables dynamic transition to the second mode. An escape indication may be enabled during the second mode for dynamic transition back to the first mode. Programmable timing values may be used to facilitate mode transitions.
摘要翻译：包括第一和第二传输协议电路，存储器和模式控制器的接口。接口包括第一和第二物理接口类型，它们都被选择性地使能以连接一组焊盘。第一传输协议电路在第一模式中与第一类型物理接口一起操作，并且第二传输协议电路以第二模式与第二类型物理接口一起工作。存储器存储指示操作模式的模式值。模式控制器根据模式值启用物理接口类型和相应的传输协议之一。第一种模式是默认模式，模式控制器使能动态转换到第二种模式。在第二模式期间可以启用转义指示，以便动态转换回到第一模式。可编程时序值可用于促进模式转换。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式