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1. 发明授权

US5958635A Lithographic proximity correction through subset feature modification 失效
标题翻译：通过子集特征修改进行平版印刷邻近校正
公开(公告)号：US5958635A
公开(公告)日：1999-09-28
申请号：US954160
申请日：1997-10-20
申请人： Alfred John Reich , Hak-Lay Chuang , Michael E. Kling , Paul G. Y. Tsui , Kevin Lucas , James N. Conner
发明人： Alfred John Reich , Hak-Lay Chuang , Michael E. Kling , Paul G. Y. Tsui , Kevin Lucas , James N. Conner
IPC分类号： G03F1/00 , G03F1/36 , G03F7/20 , G03F9/00
CPC分类号： G03F1/36 , G03F7/70425 , Y10S430/143
摘要： Lithographic Proximity Correction (LPC) shapes are added (503) to a layer of a layout database file (501). Geometric criteria such as feature width are then used to filter the added LPC shapes (502). The LPC shapes are then modified (505) by determining which LPC shapes are within a predetermined distance from a shape in a layer of the second data base (504). The database file, including the modified LPC shapes, is then used to manufacture a set of lithographic masks (506). The lithographic masks are then used to pattern a set of wafers in the manufacture of integrated circuits (507).
摘要翻译：将平版摄影校正（LPC）形状（503）添加到布局数据库文件（501）的层中。然后使用诸如特征宽度的几何标准来过滤所添加的LPC形状（502）。然后通过确定哪个LPC形状在距第二数据库（504）的层中的形状预定距离内来修改LPC形状（505）。然后，使用数据库文件（包括修改的LPC形状）来制造一组光刻掩模（506）。然后使用光刻掩模在集成电路的制造中对一组晶片进行图案化（507）。

2. 发明授权

US5827625A Methods of designing a reticle and forming a semiconductor device therewith 失效
标题翻译：设计掩模版并与其形成半导体器件的方法
公开(公告)号：US5827625A
公开(公告)日：1998-10-27
申请号：US912601
申请日：1997-08-18
申请人： Kevin Lucas , Michael E. Kling , Bernard J. Roman , Alfred J. Reich
发明人： Kevin Lucas , Michael E. Kling , Bernard J. Roman , Alfred J. Reich
IPC分类号： G03F1/00 , G03F9/00
CPC分类号： G03F1/36
摘要： A process for designing and forming a reticle (40) as well as the manufacture of a semiconductor substrate (50) using that reticle (40). The present invention places outriggers (32, 34, 36) between features (30) in both dense and semi-dense feature patterns to assist in the patterning of device features. The width of the outriggers can be changed based on pitch and location between features in a semi-dense or dense feature pattern. In one embodiment, the outriggers can be manually or automatically inserted into the layout file after the locations of the attenuating features have been determined. The outriggers are not patterned on the substrate, but assist in forming resist features of uniform width.
摘要翻译：一种用于设计和形成掩模版（40）的方法以及使用该掩模版（40）制造半导体衬底（50）。本发明在密集和半致密特征图案中的特征（30）之间放置支架（32,34,36），以有助于图案化装置特征。外悬支架的宽度可以基于半密集或密集特征图案中的特征之间的间距和位置来改变。在一个实施例中，在已经确定衰减特征的位置之后，外伸支架可以手动地或自动地插入到布局文件中。外延支架不在基板上图案化，但有助于形成均匀宽度的抗蚀剂特征。

3. 发明授权

US06573010B2 Method and apparatus for reducing incidental exposure by using a phase shifter with a variable regulator 失效
公开(公告)号：US06573010B2
公开(公告)日：2003-06-03
申请号：US09843487
申请日：2001-04-25
申请人： Michael E. Kling , Hua-Yu Liu
发明人： Michael E. Kling , Hua-Yu Liu
IPC分类号： G03F900
CPC分类号： G03F1/30 , G03F1/36 , G03F1/70
摘要： One embodiment of the invention provides a system for reducing incidental exposure caused by phase shifting during fabrication of a semiconductor chip. The system operates by identifying a problem area of likely incidental exposure in close proximity to an existing phase shifter on a phase shifting mask, wherein the problem area includes a polysilicon line passing through a field region of the semiconductor chip. The system places an additional phase shifter into the problem area on the phase shifting mask so that a regulator within the additional phase shifter protects the polysilicon line passing through the field region. This additional phase shifter has a wider regulator than the existing phase shifter, wherein the existing phase shifter is used to expose a polysilicon line in a gate region of the semiconductor chip.

4. 发明授权

US5920487A Two dimensional lithographic proximity correction using DRC shape functions 失效
标题翻译：使用DRC形状函数的二维光刻邻近校正
公开(公告)号：US5920487A
公开(公告)日：1999-07-06
申请号：US810561
申请日：1997-03-03
申请人： Alfred J. Reich , Warren D. Grobman , Bernard J. Roman , Kevin D. Lucas , Clyde H. Browning , Michael E. Kling
发明人： Alfred J. Reich , Warren D. Grobman , Bernard J. Roman , Kevin D. Lucas , Clyde H. Browning , Michael E. Kling
IPC分类号： G03F1/00 , G03F1/36 , G03F7/20 , G06F17/50 , G03F17/50 , G03F7/26
CPC分类号： G03F1/36 , G03F7/70441 , G06F17/5068
摘要： Integrated circuit designs are continually shrinking in size. Lithographic processes are used to transfer these designs to a semiconductor substrate. These processes typically require that the exposure wavelength of light be shorter than the smallest dimension of the elements within the circuit design. When this is not the case, exposure energy such as light behaves more like a wave than a particle. Additionally, mask manufacturing, photoresist chemical diffusion, and etch effects cause pattern transfer distortions. The result is that circuit elements do not print as designed. To counter this effect the circuit designs themselves can be altered so that the final printed results better matches the initial desired design. The process of altering designs in this way is called Lithographic Proximity Correction (LPC). Square (142), cross (162), octagon (172), and hammerhead (202) serifs are added to integrated circuit designs by shape manipulation functions to perform two dimensional (2-D) LPC.
摘要翻译：集成电路设计的尺寸不断缩小。使用平版印刷工艺将这些设计转移到半导体衬底。这些过程通常要求光的曝光波长比电路设计中的元件的最小尺寸短。当不是这样的情况下，诸如光的曝光能量比颗粒更像波浪。另外，掩模制造，光致抗蚀剂化学扩散和蚀刻效应引起图案转印失真。结果是电路元件不按照设计打印。为了克服这种影响，电路设计本身可以被改变，使得最终的印刷结果更好地符合初始期望的设计。以这种方式改变设计的过程称为光刻邻近校正（LPC）。通过形状操作功能将方形（142），十字（162），八边形（172）和锤头（202）衬线添加到集成电路设计中以执行二维（2-D）LPC。

5. 发明授权

US5900340A One dimensional lithographic proximity correction using DRC shape functions 失效
标题翻译：使用DRC形状函数的一维光刻邻近校正
公开(公告)号：US5900340A
公开(公告)日：1999-05-04
申请号：US805863
申请日：1997-03-03
申请人： Alfred J. Reich , Kevin D. Lucas , Michael E. Kling , Warren D. Grobman , Bernard J. Roman
发明人： Alfred J. Reich , Kevin D. Lucas , Michael E. Kling , Warren D. Grobman , Bernard J. Roman
IPC分类号： G03F1/00 , G03F1/36 , G03F7/20 , G03F9/00
CPC分类号： G03F7/70441 , G03F1/36
摘要： Integrated circuit designs are continually shrinking in size. Lithographic processes are used to pattern these designs onto a semiconductor substrate. These processes typically require that the wavelength of exposure used during printing be significantly shorter than the smallest dimension of the elements within the circuit design. When this is not the case, the exposure radiation behaves more like a wave than a particle. Additionally, mask manufacturing, photoresist chemical diffusion and etch effects cause pattern transfer distortions. The result is that circuit elements do not print as designed. To counter this effect the designs themselves can be altered so that the final printed results better match the initial desired design. The process of altering designs in this way is called Lithographic Proximity Correction (LPC). Edge assist shapes and edge biasing features are added to integrated circuit designs by shape manipulation functions to perform one dimensional (1-D) LPC.
摘要翻译：集成电路设计的尺寸不断缩小。使用平版印刷工艺将这些设计图案化成半导体衬底。这些工艺通常要求印刷期间使用的曝光波长明显短于电路设计中元件的最小尺寸。当不是这种情况时，曝光辐射的行为比颗粒更像波。此外，掩模制造，光致抗蚀剂化学扩散和蚀刻效果引起图案转印失真。结果是电路元件不按照设计打印。为了抵消这种影响，设计本身可以被改变，使得最终的印刷结果更好地符合初始期望的设计。以这种方式改变设计的过程称为光刻邻近校正（LPC）。通过形状操作功能将边缘辅助形状和边缘偏置特征添加到集成电路设计中，以执行一维（1-D）LPC。

6. 发明授权

US06566019B2 Using double exposure effects during phase shifting to control line end shortening 有权
公开(公告)号：US06566019B2
公开(公告)日：2003-05-20
申请号：US09843498
申请日：2001-04-25
申请人： Michael E. Kling , Hua-Yu Liu
发明人： Michael E. Kling , Hua-Yu Liu
IPC分类号： G03F900
CPC分类号： G03F1/30 , G03F1/36 , G03F1/70
摘要： One embodiment of the invention provides a system that facilitates a semiconductor fabrication process to create a line end in a manner that controls line end shortening arising from optical effects, and is especially applicable in alternating aperture phase shifting. This system operates by positioning a first mask over a photoresist layer on a surface of a semiconductor wafer. This first mask includes opaque regions and transmissive regions that are organized into a first pattern that defines an unexposed line on the photoresist layer. The system then exposes the photoresist layer through the first mask. The system also positions a second mask over the photoresist layer on the surface of the semiconductor wafer. This second mask includes opaque regions and transmissive regions that are organized into a second pattern that defines an exposure region. This exposure region cuts through the unexposed line on the photoresist layer to create the line end in the unexposed line, without the optical line end shortening that arises from creating the line end with a single mask. The system then exposes the photoresist layer through the second mask.

7. 发明授权

US5849440A Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same 失效
标题翻译：用于制造和检查光刻掩模版并使用其制造半导体器件的方法
公开(公告)号：US5849440A
公开(公告)日：1998-12-15
申请号：US792670
申请日：1997-01-29
申请人： Kevin D. Lucas , Michael E. Kling , Alfred J. Reich , Chong-Cheng Fu , James Morrow
发明人： Kevin D. Lucas , Michael E. Kling , Alfred J. Reich , Chong-Cheng Fu , James Morrow
IPC分类号： G03F1/00 , G03F1/84 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F7/705 , G03F1/84 , G03F7/70433 , G03F7/70633
摘要： A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lithographic pattern (18). The dimensional difference between the reticle inspection database and the lithographic reticle is substantially equal to the process bias realized during reticle fabrication. Inspection of the lithographic reticle (20) using a reticle inspection database containing altered resolution assisting features reduces the false detection of defects and provides increased sensitivity in the reticle inspection process.
摘要翻译：一种用于制造半导体器件的工艺包括形成具有覆盖在掩模版衬底（10）上的平版印刷图案（18）的光刻掩模版（20）。在一个实施例中，掩模版检查数据库包含改变的分辨率辅助特征（30,32）以检查光刻图案（18）。标线检查数据库和光刻掩模版之间的尺寸差异基本上等于在掩模版制造期间实现的工艺偏差。使用包含改变的分辨率辅助特征的掩模版检查数据库对光刻掩模版（20）的检查减少了缺陷的错误检测并且在掩模版检查过程中提供了增加的灵敏度。

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