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1. 发明授权

US08853779B2 Process for manufacturing a power semiconductor device having charge-balance columnar structures on a non-planar surface, and corresponding power semiconductor device 有权
公开(公告)号：US08853779B2
公开(公告)日：2014-10-07
申请号：US13434686
申请日：2012-03-29
申请人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L21/20 , H01L29/739 , H01L29/872 , H01L21/324 , H01L29/861 , H01L29/417 , H01L29/08 , H01L29/10
CPC分类号： H01L29/0634 , H01L21/2003 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.

2. 发明申请

US20120187480A1 PROCESS FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE HAVING CHARGE-BALANCE COLUMNAR STRUCTURES ON A NON-PLANAR SURFACE, AND CORRESPONDING POWER SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造在非平面表面上具有电荷平衡柱结构的功率半导体器件的工艺以及相应的功率半导体器件
公开(公告)号：US20120187480A1
公开(公告)日：2012-07-26
申请号：US13434741
申请日：2012-03-29
申请人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L29/78
CPC分类号： H01L29/0634 , H01L21/2003 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
摘要翻译：用于制造功率半导体器件的方法的实施例设想了以下步骤：提供具有顶表面并具有第一导电性的半导体材料体; 在半导体材料的主体内形成具有第二导电类型的柱状区域，以及在顶表面上方的柱状区域的表面延伸; 以及在顶表面附近形成具有第二类型导电性的掺杂区域并与柱状区域接触。掺杂区域至少部分地形成在柱状区域的表面延伸部内; 表面延伸部分和掺杂区域具有非平面的表面图案，特别是具有大致V形的凹槽。

3. 发明授权

US08866223B2 Process for manufacturing a power semiconductor device having charge-balance columnar structures on a non-planar surface, and corresponding power semiconductor device 有权
标题翻译：用于制造在非平面表面上具有电荷平衡柱状结构的功率半导体器件的工艺及相应的功率半导体器件
公开(公告)号：US08866223B2
公开(公告)日：2014-10-21
申请号：US13434741
申请日：2012-03-29
申请人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/417 , H01L29/872 , H01L29/861 , H01L29/10 , H01L21/20 , H01L21/324
CPC分类号： H01L29/0634 , H01L21/2003 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
摘要翻译：用于制造功率半导体器件的方法的实施例设想了以下步骤：提供具有顶表面并具有第一导电性的半导体材料体; 在半导体材料的主体内形成具有第二导电类型的柱状区域，以及在顶表面上方的柱状区域的表面延伸; 以及在顶表面附近形成具有第二类型导电性的掺杂区域并与柱状区域接触。掺杂区域至少部分地形成在柱状区域的表面延伸部内; 表面延伸部分和掺杂区域具有非平面表面图案，特别是具有大致V形凹槽。

4. 发明授权

US08455318B2 Process for manufacturing a power semiconductor device having charge-balance columnar structures on a non-planar surface, and corresponding power semiconductor device 有权
标题翻译：用于制造在非平面表面上具有电荷平衡柱状结构的功率半导体器件的工艺及相应的功率半导体器件
公开(公告)号：US08455318B2
公开(公告)日：2013-06-04
申请号：US12298025
申请日：2006-04-21
申请人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/0634 , H01L21/2003 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
摘要翻译：用于制造功率半导体器件的方法的实施例设想了以下步骤：提供具有顶表面并具有第一导电性的半导体材料体; 在半导体材料的主体内形成具有第二导电类型的柱状区域，以及在顶表面上方的柱状区域的表面延伸; 以及在顶表面附近形成具有第二类型导电性的掺杂区域并与柱状区域接触。掺杂区域至少部分地形成在柱状区域的表面延伸部内; 表面延伸部分和掺杂区域具有非平面的表面图案，特别是具有大致V形的凹槽。

5. 发明申请

US20120187479A1 PROCESS FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE HAVING CHARGE-BALANCE COLUMNAR STRUCTURES ON A NON-PLANAR SURFACE, AND CORRESPONDING POWER SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20120187479A1
公开(公告)日：2012-07-26
申请号：US13434686
申请日：2012-03-29
申请人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L29/78
CPC分类号： H01L29/0634 , H01L21/2003 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.

6. 发明申请

US20090179263A1 PROCESS FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE HAVING CHARGE-BALANCE COLUMNAR STRUCTURES ON A NON-PLANAR SURFACE, AND CORRESPONDING POWER SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造在非平面表面上具有电荷平衡柱结构的功率半导体器件的工艺以及相应的功率半导体器件
公开(公告)号：US20090179263A1
公开(公告)日：2009-07-16
申请号：US12298025
申请日：2006-04-21
申请人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L27/088 , H01L21/336 , H01L29/78
CPC分类号： H01L29/0634 , H01L21/2003 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
摘要翻译：用于制造功率半导体器件的方法的实施例设想了以下步骤：提供具有顶表面并具有第一导电性的半导体材料体; 在半导体材料的主体内形成具有第二导电类型的柱状区域，以及在顶表面上方的柱状区域的表面延伸; 以及在顶表面附近形成具有第二类型导电性的掺杂区域并与柱状区域接触。掺杂区域至少部分地形成在柱状区域的表面延伸部内; 表面延伸部分和掺杂区域具有非平面的表面图案，特别是具有大致V形的凹槽。

7. 发明授权

US08901652B2 Power MOSFET comprising a plurality of columnar structures defining the charge balancing region 有权
标题翻译：功率MOSFET包括限定电荷平衡区域的多个柱状结构
公开(公告)号：US08901652B2
公开(公告)日：2014-12-02
申请号：US12862976
申请日：2010-08-25
申请人： Mario Giuseppe Saggio , Alfio Guarnera , Simone Rascuna′
发明人： Mario Giuseppe Saggio , Alfio Guarnera , Simone Rascuna′
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0878 , H01L29/42368 , H01L29/7811
摘要： An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:—an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;—an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.
摘要翻译：一种用于集成在半导体衬底上的第一类导电性的功率器件的半导体结构的实施例，包括： - 在所述半导体衬底上形成所述第一导电类型的外延层，并且具有多个柱结构，第二类型的导电性，以限定电荷平衡区域; - 在所述外延层上形成的用于容纳多个有源区域的有源表面层; 所述外延层包括布置在电荷平衡区域和有源表面层之间的半导体分离层，所述半导体分离层将所述柱结构与所述有源区域分离。

8. 发明授权

US08455956B2 Multi-drain semiconductor power device and edge-termination structure thereof 有权
标题翻译：多漏极半导体功率器件及其边沿端接结构
公开(公告)号：US08455956B2
公开(公告)日：2013-06-04
申请号：US12640980
申请日：2009-12-17
申请人： Mario Giuseppe Saggio , Alfio Guarnera
发明人： Mario Giuseppe Saggio , Alfio Guarnera
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/761 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/7811
摘要： An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.
摘要翻译：一种半导体功率器件的实施例，其具备：由具有第一导电性的半导体材料制成的结构体，其具有容纳一个或多个基本电子部件的有源区域和在有源区域外部限定的边缘区域; 并且由掺杂有与第一导电性相反的第二导电性的区域构成的电荷平衡结构在有源区域和边缘区域中延伸穿过结构体，以产生实质的电荷平衡。电荷平衡结构是在活性区域和边缘区域中彼此平行延伸的柱状壁，而没有任何相互交叉。

9. 发明授权

US08039898B2 Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device 有权
标题翻译：用于制造电荷平衡功率二极管的工艺和用于电荷平衡半导体功率器件的边缘终端结构
公开(公告)号：US08039898B2
公开(公告)日：2011-10-18
申请号：US11824169
申请日：2007-06-28
申请人： Mario Giuseppe Saggio , Domenico Murabito , Ferruccio Frisina
发明人： Mario Giuseppe Saggio , Domenico Murabito , Ferruccio Frisina
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L21/324 , H01L29/0615 , H01L29/0634 , H01L29/0661 , H01L29/0692 , H01L29/0847 , H01L29/41766 , H01L29/66128 , H01L29/66727 , H01L29/66734 , H01L29/73 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically coupled to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region. The process further envisages the steps of: forming a surface layer having the first type of conductivity on the first top surface, also at the peripheral edge portion, in contact with the guard region; and etching the surface layer in order to remove it above the edge portion in such a manner that the etch terminates inside the guard region.
摘要翻译：制造半导体功率器件的方法的一个实施例设想了以下步骤：提供由具有第一顶表面的半导体材料制成的本体; 在所述第一顶表面附近和所述主体的活动部分内部形成具有第一类型导电性的有源区; 并形成边缘终端结构。边缘终端结构由以下部分形成：具有第一类型的导电性和第一掺杂水平的环形区域，其设置在主体的外围边缘部分内并电耦合到有源区域; 以及保护区，其具有高于第一掺杂级的第一类型的导电性和第二掺杂级，设置在第一顶表面附近并将有源区连接到环区。该方法进一步设想了以下步骤：在第一顶表面上形成具有第一类型导电性的表面层，也在周边边缘部分形成与保护区域接触的表面层; 并且蚀刻表面层以便以这样的方式将其去除边缘部分，使得蚀刻终止于保护区域内。

10. 发明授权

US07871880B2 Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices 有权
标题翻译：用于制造集成在半导体衬底中的电子器件和相应器件的方法
公开(公告)号：US07871880B2
公开(公告)日：2011-01-18
申请号：US11971155
申请日：2008-01-08
申请人： Ferruccio Frisina , Mario Giuseppe Saggio
发明人： Ferruccio Frisina , Mario Giuseppe Saggio
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/44 , H01L21/28
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1608 , H01L29/42368 , H01L29/66068
摘要： A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions.
摘要翻译：一种制造半导体衬底上的垂直功率MOS晶体管的方法，包括：第一导电类型的第一表面半导体层，包括：在第一半导体层中形成沟槽区，用第二导电类型的第二半导体层填充所述沟槽区，以形成包含在第一半导体层中的第二导电类型的半导体部分，在用于形成所述第二导电类型的各个植入体区域的半导体部分中执行第一掺杂剂类型的离子注入，进行离子注入一个植入体区域中的第二掺杂剂类型，用于在一个体区内形成第一导电类型的注入源区域，进行适于完成所述形成的具有低热预算的第一和第二掺杂剂类型的活化热处理的身体和来源地区。

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