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    • 5. 发明授权
    • Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating
    • 具有易失性和多位,非易失性功能和操作方法的半导体存储器
    • US08923052B2
    • 2014-12-30
    • US13196471
    • 2011-08-02
    • Yuniarto Widjaja
    • Yuniarto Widjaja
    • G11C11/34G11C14/00H01L27/105H01L27/108H01L29/78H01L27/115G11C16/04
    • G11C14/0018G11C11/5671G11C14/00G11C16/02G11C16/0466G11C16/0475H01L27/105H01L27/108H01L27/10802H01L27/115H01L29/7841H01L29/792
    • A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another, and a control gate positioned above the trapping layer.
    • 描述了半导体存储单元,包括多个半导体存储单元的半导体存储器件以及使用该半导体存储单元和器件的方法。 半导体存储单元包括具有第一导电类型的衬底; 第一区域,其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域,其在衬底的第二位置处嵌入在衬底中并具有第二导电类型,使得具有第一导电类型的衬底的至少一部分位于第一和第二位置之间,并且用作浮体 将数据存储在易失性存储器中; 位于所述第一位置和所述第二位置之间并位于所述衬底的表面之上的捕获层; 包括第一和第二存储位置的捕获层被配置为将数据彼此独立地存储为非易失性存储器,以及位于捕获层上方的控制栅极。