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1. 发明申请

US20120054519A1 DYNAMIC PERFORMANCE CONTROL OF PROCESSING NODES 有权
标题翻译：加工过程动态性能控制
公开(公告)号：US20120054519A1
公开(公告)日：2012-03-01
申请号：US12868996
申请日：2010-08-26
申请人： Alexander Branover , Maurice Steinman , William L. Bircher
发明人： Alexander Branover , Maurice Steinman , William L. Bircher
IPC分类号： G06F1/32
CPC分类号： G06F1/3215 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.
摘要翻译：公开了一种用于处理节点的性能控制的装置和方法。在一个实施例中，系统包括处理节点和功率管理单元，其被配置为针对多个时间间隔中的每一个监视处理节点的活动级别，使处理节点在连续的连续操作期间在高操作点时间间隔，如果给定间隔中的活动水平大于高活动阈值，则如果活动水平低于低活动阈值，则在低操作点操作至少一个连续时间间隔，或使得操作系统软件能够使处理节点在多个操作点的一个或多个预定义的中间操作点之一操作，如果活动水平小于高活动阈值并且大于低活动阈值。

2. 发明授权

US08484498B2 Method and apparatus for demand-based control of processing node performance 有权
标题翻译：用于基于需求的处理节点性能控制的方法和装置
公开(公告)号：US08484498B2
公开(公告)日：2013-07-09
申请号：US12868996
申请日：2010-08-26
申请人： Alexander Branover , Maurice Steinman , William L. Bircher
发明人： Alexander Branover , Maurice Steinman , William L. Bircher
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3215 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.
摘要翻译：公开了一种用于处理节点的性能控制的装置和方法。在一个实施例中，系统包括处理节点和功率管理单元，其被配置为针对多个时间间隔中的每一个监视处理节点的活动级别，使得处理节点在连续的连续操作期间在高操作点时间间隔，如果给定间隔中的活动水平大于高活动阈值，则如果活动水平低于低活动阈值，则在低操作点操作至少一个连续时间间隔，或使得操作系统软件能够使处理节点在多个操作点的一个或多个预定义的中间操作点之一操作，如果活动水平小于高活动阈值并且大于低活动阈值。

3. 发明授权

US08156362B2 Hardware monitoring and decision making for transitioning in and out of low-power state 有权
标题翻译：硬件监控和决策过渡进出低功耗状态
公开(公告)号：US08156362B2
公开(公告)日：2012-04-10
申请号：US12198974
申请日：2008-08-27
申请人： Alexander Branover , Frank Helms , Maurice Steinman
发明人： Alexander Branover , Frank Helms , Maurice Steinman
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.
摘要翻译：与包括一个或多个核心的处理器连接的电源管理控制器（PMC）。 PMC可以被配置为与每个相应的核心通信，使得由相应的处理器核心执行的微代码可以识别什么时候进行请求以将各个核心转换到目标功率状态。对于每个相应的核心，状态监视器可以监视与相应核心的相关联的活动状态驻留，非活动状态驻留，直接存储器访问（DMA）传送活动，与相应核心相关联的输入/输出（I / O）过程，以及与相应核心相关联的定时器 - 刻度（TT）间隔的值。状态监视器可以基于监视导出各个核心的各自的状态信息，并且指示是否应允许相应的核心转换到对应的目标功率状态。 PMC可以相应地将相应的处理器核心转变到相应的目标功率状态。

4. 发明申请

US20090235105A1 Hardware Monitoring and Decision Making for Transitioning In and Out of Low-Power State 有权
标题翻译：硬件监控和决策过渡进出低功耗状态
公开(公告)号：US20090235105A1
公开(公告)日：2009-09-17
申请号：US12198974
申请日：2008-08-27
申请人： Alexander Branover , Frank Helms , Maurice Steinman
发明人： Alexander Branover , Frank Helms , Maurice Steinman
IPC分类号： G06F1/26 , G06F13/28 , G06F13/24
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.
摘要翻译：与包括一个或多个核心的处理器连接的电源管理控制器（PMC）。 PMC可以被配置为与每个相应的核心通信，使得由相应的处理器核心执行的微代码可以识别什么时候进行请求以将各个核心转换到目标功率状态。对于每个相应的核心，状态监视器可以监视与相应核心的相关联的活动状态驻留，非活动状态驻留，直接存储器访问（DMA）传送活动，与相应核心相关联的输入/输出（I / O）过程，以及与相应核心相关联的定时器 - 刻度（TT）间隔的值。状态监视器可以基于监视导出各个核心的各自的状态信息，并且指示是否应允许相应的核心转换到对应的目标功率状态。 PMC可以相应地将相应的处理器核心转变到相应的目标功率状态。

5. 发明申请

US20080276026A1 SELECTIVE DEACTIVATION OF PROCESSOR CORES IN MULTIPLE PROCESSOR CORE SYSTEMS 有权
标题翻译：在多个处理器核心系统中选择性地消除处理器线
公开(公告)号：US20080276026A1
公开(公告)日：2008-11-06
申请号：US11743341
申请日：2007-05-02
申请人： Alexander Branover , Maurice Steinman , Frank Helms , Bill K.C. Kwan , W. Kurt Lewchuk , Paul Mackey
发明人： Alexander Branover , Maurice Steinman , Frank Helms , Bill K.C. Kwan , W. Kurt Lewchuk , Paul Mackey
IPC分类号： G06F13/24
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.
摘要翻译：一种方法包括将电压施加到多个处理器核心的第一处理器核心以去激活第一处理器核心，该电压小于第一处理器核心的保持电压。电压的应用可以响应于软件设置。可以通过用户输入，软件应用程序，操作系统或BIOS设置来配置软件设置。或者，电压的施加可以响应于诸如与第一处理器核心相关联的保险丝的状态的永久硬件设置。

6. 发明授权

US07856562B2 Selective deactivation of processor cores in multiple processor core systems 有权
标题翻译：在多个处理器核心系统中选择性地禁用处理器内核
公开(公告)号：US07856562B2
公开(公告)日：2010-12-21
申请号：US11743341
申请日：2007-05-02
申请人： Alexander Branover , Maurice Steinman , Frank Helms , Bill K. C. Kwan , W. Kurt Lewchuk , Paul Mackey
发明人： Alexander Branover , Maurice Steinman , Frank Helms , Bill K. C. Kwan , W. Kurt Lewchuk , Paul Mackey
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.
摘要翻译：一种方法包括将电压施加到多个处理器核心的第一处理器核心以去激活第一处理器核心，该电压小于第一处理器核心的保持电压。电压的应用可以响应于软件设置。可以通过用户输入，软件应用程序，操作系统或BIOS设置来配置软件设置。或者，电压的施加可以响应于诸如与第一处理器核心相关联的保险丝的状态的永久硬件设置。

7. 发明申请

US20080276236A1 DATA PROCESSING DEVICE WITH LOW-POWER CACHE ACCESS MODE 有权
标题翻译：具有低功耗高速缓存访问模式的数据处理设备
公开(公告)号：US20080276236A1
公开(公告)日：2008-11-06
申请号：US11743388
申请日：2007-05-02
申请人： Alex Branover , Frank P. Helms , Maurice Steinman
发明人： Alex Branover , Frank P. Helms , Maurice Steinman
IPC分类号： G06F9/46
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3243 , G06F1/3275 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/152 , Y02D10/171 , Y02D10/172
摘要： A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode.
摘要翻译：处理器可以在三种不同的模式下工作。在活动模式中，向处理器提供第一电压，其中第一电压足以允许处理器执行指令。在低功率模式下，向处理器提供保持电压。处理器在保留模式下的功耗比活动模式低。此外，处理器可以在第三模式下操作，其中向处理器提供足够的电压以允许处理器处理诸如一致性消息之类的缓存消息，但不执行其他正常操作或以非常低的速度执行正常操作相对于他们在活动模式下的表现。

8. 发明申请

US20050281203A1 Methods and apparatuses for detecting clock failure and establishing an alternate clock lane 有权
标题翻译：用于检测时钟故障并建立备用时钟通道的方法和装置
公开(公告)号：US20050281203A1
公开(公告)日：2005-12-22
申请号：US10874511
申请日：2004-06-22
申请人： Naveen Cherukuri , Tim Frodsham , Eduard Roytman , Sanjay Dabral , Rahul Shah , Theodore Schoenborn , Maurice Steinman , David Dunning
发明人： Naveen Cherukuri , Tim Frodsham , Eduard Roytman , Sanjay Dabral , Rahul Shah , Theodore Schoenborn , Maurice Steinman , David Dunning
IPC分类号： H04J3/06 , H04L12/26
CPC分类号： H04J3/0688 , H04L43/00 , H04L43/0847
摘要： Methods and apparatuses for determining clock failure for a multi-agent system employing a link-based interconnection scheme using a forwarded clock. For one embodiment of the invention, the cessation of the forwarded clock initiates a clock failure determination process. For one embodiment of the invention, upon a determination of clock failure, an alternate clock lane is implemented using a pre-designated data lane.
摘要翻译：用于确定使用转发时钟的基于链路的互连方案的多代理系统的时钟故障的方法和装置。对于本发明的一个实施例，转发时钟的停止启动时钟失败确定过程。对于本发明的一个实施例，在确定时钟故障时，使用预先指定的数据通道实现备用时钟通道。

9. 发明授权

US07870407B2 Dynamic processor power management device and method thereof 有权
标题翻译：动态处理器电源管理装置及其方法
公开(公告)号：US07870407B2
公开(公告)日：2011-01-11
申请号：US11750365
申请日：2007-05-18
申请人： Alex Branover , Frank P. Helms , Jonathan M. Owen , Kurt Lewchuk , Maurice Steinman , Paul Mackey
发明人： Alex Branover , Frank P. Helms , Jonathan M. Owen , Kurt Lewchuk , Maurice Steinman , Paul Mackey
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.
摘要翻译：处理器可以在不同的功率模式下工作。在有功功率模式下，处理器执行软件。响应于从软件接收到停止指示，处理器处的硬件评估处理器的总线事务。如果总线事务满足启发式，则硬件将处理器内核置于较低功耗模式下，例如保留模式。由于总线事务由硬件而不是软件进行评估，并且软件不需要执行握手和其他协议来将处理器置于低功耗模式，处理器能够将处理器内核置于低功耗模式更快，从而节约电力。

10. 发明授权

US07941683B2 Data processing device with low-power cache access mode 有权
标题翻译：具有低功耗缓存访问模式的数据处理设备
公开(公告)号：US07941683B2
公开(公告)日：2011-05-10
申请号：US11743388
申请日：2007-05-02
申请人： Alex Branover , Frank P. Helms , Maurice Steinman
发明人： Alex Branover , Frank P. Helms , Maurice Steinman
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3243 , G06F1/3275 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/152 , Y02D10/171 , Y02D10/172
摘要： A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode.
摘要翻译：处理器可以在三种不同的模式下工作。在活动模式中，向处理器提供第一电压，其中第一电压足以允许处理器执行指令。在低功率模式下，向处理器提供保持电压。处理器在保留模式下的功耗比活动模式低。此外，处理器可以在第三模式下操作，其中向处理器提供足够的电压以允许处理器处理诸如一致性消息之类的缓存消息，但不执行其他正常操作或以非常低的速度执行正常操作相对于他们在活动模式下的表现。

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