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1. 发明授权

US09257410B2 Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate 有权
标题翻译：包含半导体衬底的封装组件，其中半导体衬底的表面的第一部分相对于半导体衬底的表面的第二部分凹陷，以在半导体衬底中形成凹陷区域
公开(公告)号：US09257410B2
公开(公告)日：2016-02-09
申请号：US13012644
申请日：2011-01-24
申请人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
发明人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
IPC分类号： H01L25/04 , H01L21/48 , H01L23/13 , H01L23/14 , H01L23/498 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/367 , H01L23/00
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种装置，包括具有第一表面的半导体衬底，与第一表面相对设置的第二表面，其中第一表面的至少一部分被凹入以形成半导体衬底的凹陷区域，以及形成在半导体衬底的凹陷区域中以在半导体衬底的第一表面和第二表面之间提供电或热路径的一个或多个通孔，以及耦合到半导体衬底的管芯，该管芯电耦合到形成在半导体衬底的凹陷区域中的一个或多个通孔。可以描述和/或要求保护其他实施例。

2. 发明授权

US09034730B2 Recessed semiconductor substrates and associated techniques 有权
标题翻译：嵌入式半导体衬底及相关技术
公开(公告)号：US09034730B2
公开(公告)日：2015-05-19
申请号：US13015988
申请日：2011-01-28
申请人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
发明人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
IPC分类号： H01L21/762 , H01L25/04 , H01L21/48 , H01L23/13 , H01L23/14 , H01L23/498 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/367 , H01L23/00
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供一种方法，包括提供半导体衬底，其具有（i）第一表面和（ii）与第一表面相对设置的第二表面，在半导体衬底的第一表面中形成一个或多个通孔一个或多个通孔最初仅通过半导体衬底的一部分而不到达第二表面，在半导体衬底的第一表面上形成电介质膜，在电介质膜上形成再分布层，再分配层电耦合连接到所述一个或多个通孔，将一个或多个管芯耦合到所述再分布层，形成模制化合物以封装所述一个或多个管芯的至少一部分，以及使所述半导体衬底的所述第二表面凹陷以暴露所述一个或多个通孔。可以描述和/或要求保护其他实施例。

3. 发明申请

US20110186992A1 RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES 有权
标题翻译：残留的半导体衬底和相关技术
公开(公告)号：US20110186992A1
公开(公告)日：2011-08-04
申请号：US13015988
申请日：2011-01-28
申请人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
发明人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供一种方法，包括提供半导体衬底，其具有（i）第一表面和（ii）与第一表面相对设置的第二表面，在半导体衬底的第一表面中形成一个或多个通孔一个或多个通孔最初仅通过半导体衬底的一部分而不到达第二表面，在半导体衬底的第一表面上形成电介质膜，在电介质膜上形成再分布层，再分配层电耦合连接到所述一个或多个通孔，将一个或多个管芯耦合到所述再分布层，形成模制化合物以封装所述一个或多个管芯的至少一部分，以及使所述半导体衬底的所述第二表面凹陷以暴露所述一个或多个通孔。可以描述和/或要求保护其他实施例。

4. 发明申请

US20110186998A1 RECESSED SEMICONDUCTOR SUBSTRATES 有权
标题翻译：残留的半导体衬底
公开(公告)号：US20110186998A1
公开(公告)日：2011-08-04
申请号：US13012644
申请日：2011-01-24
申请人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
发明人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种装置，包括具有第一表面的半导体衬底，与第一表面相对设置的第二表面，其中第一表面的至少一部分被凹入以形成半导体衬底的凹陷区域，以及形成在半导体衬底的凹陷区域中以在半导体衬底的第一表面和第二表面之间提供电或热路径的一个或多个通孔以及耦合到半导体衬底的管芯，该管芯电耦合到形成在半导体衬底的凹陷区域中的一个或多个通孔。可以描述和/或要求保护其他实施例。

5. 发明申请

US20110186960A1 TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：接触半导体衬底的技术和配置
公开(公告)号：US20110186960A1
公开(公告)日：2011-08-04
申请号：US13007059
申请日：2011-01-14
申请人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
发明人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
IPC分类号： H01L27/04 , H01L23/488 , H01L21/60 , H01L21/98
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种方法，包括提供具有（i）第一表面和（ii）与第一表面相对设置的第二表面的半导体衬底，在半导体衬底的第一表面上形成电介质膜，形成电介质膜上的再分配层，将一个或多个管芯电耦合到再分布层，在半导体衬底上形成模制化合物，使半导体衬底的第二表面凹陷，通过半导体的凹陷的第二表面形成一个或多个沟道衬底以暴露再分布层; 以及在所述一个或多个通道中形成一个或多个封装互连结构，所述一个或多个封装互连结构电耦合到所述再分布层，所述一个或多个封装互连结构用于布置所述一个或多个管芯的电信号。可以描述和/或要求保护其他实施例。

6. 发明申请

US20110175218A1 PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：具有半导体基板的封装组件
公开(公告)号：US20110175218A1
公开(公告)日：2011-07-21
申请号：US12973249
申请日：2010-12-20
申请人： Shiann-Ming Liou , Sehat Sutardja , Albert Wu , Chuan-Cheng Cheng , Chien-Chuan Wei
发明人： Shiann-Ming Liou , Sehat Sutardja , Albert Wu , Chuan-Cheng Cheng , Chien-Chuan Wei
IPC分类号： H01L23/34 , H01L21/60
CPC分类号： H01L23/42 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/60 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/1403 , H01L2224/14181 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12035 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种方法，其包括提供包括半导体材料的半导体衬底，在半导体衬底上形成电介质层，在电介质层上形成互连层，将半导体管芯附着到半导体衬底上，半导体管芯的有源侧到互连层，互连层以引导半导体管芯的电信号。可以描述和/或要求保护其他实施例。

7. 发明申请

US20120098127A1 POWER/GROUND LAYOUT FOR CHIPS 有权
标题翻译：电源/接地布局
公开(公告)号：US20120098127A1
公开(公告)日：2012-04-26
申请号：US13277140
申请日：2011-10-19
申请人： Sehat Sutardja , Chung Chyung Han , Weidan Li , Shuhua Yu , Chuan-Cheng Cheng , Albert Wu
发明人： Sehat Sutardja , Chung Chyung Han , Weidan Li , Shuhua Yu , Chuan-Cheng Cheng , Albert Wu
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L21/76885 , H01L23/3107 , H01L23/5226 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/061 , H01L2224/16145 , H01L2224/16245 , H01L2224/45111 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/731 , H01L2224/85 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
摘要翻译：本公开的实施例提供一种芯片，其包括形成在第一半导体管芯上的基底金属层和形成在基底金属层上的第一金属层。第一金属层包括被配置为路由芯片中的（i）接地信号或（ii）功率信号中的至少一个的多个岛。芯片还包括形成在第一金属层上的第二金属层。第二金属层包括被配置为路由（i）接地信号或（ii）芯片中的功率信号中的至少一个的多个岛。

8. 发明授权

US08946890B2 Power/ground layout for chips 有权
标题翻译：芯片的电源/接地布局
公开(公告)号：US08946890B2
公开(公告)日：2015-02-03
申请号：US13277140
申请日：2011-10-19
申请人： Sehat Sutardja , Chung Chyung Han , Weidan Li , Shuhua Yu , Chuan-Cheng Cheng , Albert Wu
发明人： Sehat Sutardja , Chung Chyung Han , Weidan Li , Shuhua Yu , Chuan-Cheng Cheng , Albert Wu
IPC分类号： H01L23/498 , H01L23/00 , H01L23/522 , H01L23/528 , H01L25/065 , H01L25/00 , H01L23/31
CPC分类号： H01L21/76885 , H01L23/3107 , H01L23/5226 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/061 , H01L2224/16145 , H01L2224/16245 , H01L2224/45111 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/731 , H01L2224/85 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
摘要翻译：本公开的实施例提供一种芯片，其包括形成在第一半导体管芯上的基底金属层和形成在基底金属层上的第一金属层。第一金属层包括被配置为路由芯片中的（i）接地信号或（ii）功率信号中的至少一个的多个岛。芯片还包括形成在第一金属层上的第二金属层。第二金属层包括被配置为路由（i）接地信号或（ii）芯片中的功率信号中的至少一个的多个岛。

9. 发明授权

US07939445B1 High density via and metal interconnect structures, and methods of forming the same 有权
标题翻译：高密度通孔和金属互连结构及其形成方法
公开(公告)号：US07939445B1
公开(公告)日：2011-05-10
申请号：US12049229
申请日：2008-03-14
申请人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Pantas Sutardja , Albert Wu , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838
摘要： Methods and structures for interconnects in semiconductor devices are described. A method of forming a mask pattern for a metal layer in an interconnect can include searching a layout for a metal feature with a predetermined size and an interconnect layer aligned thereto, removing the metal feature from the layout to form a modified layout, and reforming the mask pattern using the modified layout. The metal interconnect may include a first pattern of metal lines, each having a minimum feature size in a layout view in no more than one dimension; a dielectric layer on or over the first pattern of metal lines, having a substantially planar horizontal upper surface; and vias or contacts in the dielectric layer, the vias or contacts contacting a top surface of the first pattern of metal lines and a top surface of silicon structures, vias, or contacts below the first pattern of metal lines.
摘要翻译：描述了半导体器件中互连的方法和结构。在互连中形成用于金属层的掩模图案的方法可以包括搜索具有预定尺寸的金属特征的布局和与其对准的互连层，从布局去除金属特征以形成修改的布局，并且重新形成掩模图案使用修改的布局。金属互连可以包括金属线的第一图案，每个金属线在布局视图中具有不超过一个维度的最小特征尺寸; 金属线的第一图案上或之上的介电层，具有基本上平面的水平上表面; 以及电介质层中的通孔或触点，接触金属线的第一图案的顶表面的通孔或触点以及金属线的第一图案之下的硅结构，通孔或触点的顶表面。

10. 发明授权

US08999786B1 Reducing source contact to gate spacing to decrease transistor pitch 有权
标题翻译：将源触点减小到栅极间距，以减小晶体管间距
公开(公告)号：US08999786B1
公开(公告)日：2015-04-07
申请号：US12052573
申请日：2008-03-20
申请人： Albert Wu , Pantas Sutardja , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
发明人： Albert Wu , Pantas Sutardja , Winston Lee , Peter Lee , Chien-Chuan Wei , Runzi Chang
IPC分类号： H01L21/336 , H01L29/788 , H01L21/027
CPC分类号： H01L29/41775 , H01L21/027 , H01L21/823425 , H01L27/11568 , H01L29/0847 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7835 , H01L29/792
摘要： Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.
摘要翻译：公开了具有减小的半导体器件中与栅极间隔的源极接触的晶体管的方法和结构。在一个实施例中，形成晶体管的方法可以包括：在晶体管的有源区上形成栅极; 形成与有源区域中的栅极对准的源区和漏区; 在源极和漏极区域上形成源极和漏极接触，其中晶体管的栅极至源极接触的间隔小于晶体管的栅极至漏极接触的间隔; 并且使用一个或多个修改的掩模来形成源极区和漏极区的掺杂分布。

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