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1. 发明授权

US06385692B2 Methods and apparatus for variable length SDRAM transfers 有权
标题翻译：用于可变长度SDRAM传输的方法和装置
公开(公告)号：US06385692B2
公开(公告)日：2002-05-07
申请号：US09805588
申请日：2001-03-12
申请人： Jano D. Banks , Dale R. Adams , Albert M. Scalise
发明人： Jano D. Banks , Dale R. Adams , Albert M. Scalise
IPC分类号： G06F1200
CPC分类号： G06F13/1647 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in progress, a write in progress, or idle. The data control state machine then handles the memory request with a different bank of memory RAM depending upon the current state of the first bank of memory.
摘要翻译：公开了一种SDRAM系统，包括具有多组存储器的SDRAM，与SDRAM的多组存储器相关联的多个存储体状态机以及数据控制状态机。数据状态机响应于与SDRAM以及银行状态机的可变长度数据传输的存储器请求。数据控制状态机确定SDRAM的第一存储体的当前状态。当前状态可能是正在读取，正在进行中或空闲。然后，数据控制状态机根据第一存储器组的当前状态来处理具有不同存储器RAM组的存储器请求。

2. 发明授权

US06393505B1 Methods and apparatus for data bus arbitration 有权
标题翻译：数据总线仲裁的方法和装置
公开(公告)号：US06393505B1
公开(公告)日：2002-05-21
申请号：US09227502
申请日：1999-01-06
申请人： Albert M. Scalise , Jano D. Banks
发明人： Albert M. Scalise , Jano D. Banks
IPC分类号： G06F1300
CPC分类号： G06F13/161 , G06F13/364
摘要： A data bus arbitration system is disclosed including a bus status monitor which is coupled to a data bus and generates a bus status signal for use by an arbiter. The arbiter is coupled to a number of requesters, each of which belongs to a distinct class of requesters. The arbiter arbitrates between multiple requests using heuristics dependent upon the classes of the requesters. The nature of one class of requestors is that the requestors have real time requirements which must be met in order to maintain data integrity within the system. The nature of a second class of requestors is such that the requestors have semi-real time requirements which must be met in order to maintain data integrity within the system. The nature of the system is such that the available bandwidth must be utilized very efficiently in order to maintain data integrity within the system. The arbiter system disclosed grants access to the requesters using the heuristics disclosed while maintaining an efficiency of at least 80% of the total bandwidth for all requestors.
摘要翻译：公开了一种数据总线仲裁系统，其包括耦合到数据总线的总线状态监视器，并产生总线状态信号供仲裁器使用。仲裁器耦合到一些请求者，每个请求者属于不同类别的请求者。仲裁者根据请求者的类别使用启发式方式在多个请求之间进行仲裁。一类请求者的性质是请求者具有必须满足的实时要求，以便保持系统内的数据完整性。第二类请求者的性质使得请求者具有必须满足的半实时要求，以便保持系统内的数据完整性。系统的性质使得必须非常有效地利用可用的带宽，以便保持系统内的数据完整性。所公开的仲裁系统使用所公开的启发式方式来访问请求者，同时保持所有请求者的总带宽的至少80％的效率。

3. 发明授权

US09640067B1 Determining commands on a media device interface 有权
公开(公告)号：US09640067B1
公开(公告)日：2017-05-02
申请号：US13602794
申请日：2012-09-04
申请人： Albert M. Scalise , Jano D. Banks , Andrew S. Brenner , Christopher D. Painter
发明人： Albert M. Scalise , Jano D. Banks , Andrew S. Brenner , Christopher D. Painter
IPC分类号： G08C19/00
CPC分类号： G08C19/00 , G08C17/02 , G08C2201/20 , G08C2201/21
摘要： Described herein are systems and methods for a media controller configured to associate data from a media device received using a media device interface with actions on the media devices. The associated data and actions may be used to build a media device interface command map. The media device interface command map may be used by the media controller to control the media device. A user interface provided by the media controller may thus be used to control disparate devices, allowing for a coordinated and consistent user experience across multiple media devices, even when they are from different manufacturers.

4. 发明授权

US06219747B1 Methods and apparatus for variable length SDRAM transfers 有权
标题翻译：用于可变长度SDRAM传输的方法和装置
公开(公告)号：US06219747B1
公开(公告)日：2001-04-17
申请号：US09226776
申请日：1999-01-06
申请人： Jano D. Banks , Dale R. Adams , Albert M. Scalise
发明人： Jano D. Banks , Dale R. Adams , Albert M. Scalise
IPC分类号： G06F1200
CPC分类号： G06F13/1647 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in progress, a write in progress, or idle. The data control state machine then handles the memory request with a different bank of memory RAM depending upon the current state of the first bank of memory.
摘要翻译：公开了一种SDRAM系统，包括具有多组存储器的SDRAM，与SDRAM的多组存储器相关联的多个存储体状态机以及数据控制状态机。数据状态机响应于与SDRAM以及银行状态机的可变长度数据传输的存储器请求。数据控制状态机确定SDRAM的第一存储体的当前状态。当前状态可能是正在读取，正在进行中或空闲。然后，数据控制状态机根据第一存储器组的当前状态来处理具有不同存储器RAM组的存储器请求。

5. 发明授权

US09811878B1 Dynamic processing of image borders 有权
公开(公告)号：US09811878B1
公开(公告)日：2017-11-07
申请号：US13602566
申请日：2012-09-04
申请人： Parag K. Garg , Jano D. Banks
发明人： Parag K. Garg , Jano D. Banks
IPC分类号： G06T3/40 , H04N7/01
CPC分类号： G06T3/40 , H04N5/44591 , H04N7/007 , H04N7/0122 , H04N7/08
摘要： Described herein are systems and methods of processing images comprising border features including, but not limited to letterboxing, pillarboxing, or windowboxing. Between the border features is primary content. The processing comprises scaling the primary content to increase prominence during presentation. Space unused during the presentation is filled with a revised border. Supplemental content may be presented in at least a portion of the revised border.

6. 发明授权

US06473476B1 Method and apparatus for providing deterministic resets for clock divider systems 有权
标题翻译：用于为时钟分频器系统提供确定性复位的方法和装置
公开(公告)号：US06473476B1
公开(公告)日：2002-10-29
申请号：US09226381
申请日：1999-01-06
申请人： Jano D. Banks
发明人： Jano D. Banks
IPC分类号： H03B1900
CPC分类号： G06F1/24
摘要： A clock divider system with reset synchronization includes a divider circuit, a synchronizer circuit, and a synchronous delay circuit. The divider circuit has a clock input, a divider reset input, and a divided clock output. The synchronizer has a clock input, and a synchronous reset input, and a synchronized reset output having an active edge aligned with an active edge of the clock. The synchronous delay circuit has a clock input and a synchronized reset input coupled to the synchronized reset output of the synchronizer, and an output coupled to the divider reset input of the divider. A method for providing reset synchronization for a clock divider system includes developing a reset synchronization signal aligned with an active edge of a clock after receiving an asynchronous reset signal, delaying the reset synchronization signal for at least one cycle to provide a delayed reset synchronization signal, and developing a clock divider reset signal from the delayed reset synchronization signal, that is aligned with an active edge of the clock.
摘要翻译：具有复位同步的时钟分频器系统包括分频器电路，同步器电路和同步延迟电路。分频器电路具有时钟输入，分频复位输入和分频时钟输出。同步器具有时钟输入和同步复位输入以及具有与时钟的有效边沿对准的有效边沿的同步复位输出。同步延迟电路具有耦合到同步器的同步复位输出的时钟输入和同步复位输入，以及耦合到分频器的分频复位输入的输出。一种用于为时钟分配器系统提供复位同步的方法包括在接收到异步复位信号之后，开发与时钟的有效边沿对准的复位同步信号，延迟复位同步信号至少一个周期以提供延迟的复位同步信号，并且从延迟的复位同步信号开发与时钟的有效边沿对准的时钟分频器复位信号。

7. 发明授权

US07215376B2 Digital video system and methods for providing same 有权
标题翻译：数字视频系统及其提供方法
公开(公告)号：US07215376B2
公开(公告)日：2007-05-08
申请号：US10032136
申请日：2001-12-21
申请人： Dale R. Adams , Laurence A. Thompson , Jano D. Banks , David C. Buuck , Cheng Hwee Chee
发明人： Dale R. Adams , Laurence A. Thompson , Jano D. Banks , David C. Buuck , Cheng Hwee Chee
IPC分类号： H04N7/01 , H04N11/20
CPC分类号： B60R11/0235 , B60R11/0211 , B60R11/0252 , B60R2011/0012 , B60R2011/0017 , G06F1/1626 , G06F1/1632 , G06F1/1656 , G06F1/166 , G06T3/40 , G06T5/002 , G06T2207/10016 , G06T2207/20192 , G09G5/39 , G09G5/393 , G09G2310/0229 , H04N5/14 , H04N5/147 , H04N5/4401 , H04N5/66 , H04N5/775 , H04N5/85 , H04N7/0112 , H04N7/012 , H04N9/8042
摘要： A digital image enhancer includes a deinterlacing processor receptive to an interlaced video stream. The deinterlacing processor includes a first deinterlacer and a second deinterlacer and provides a deinterlaced video stream. The digital image enhancer also includes a video output processor receptive to the output of the deinterlaced video stream to provide a scaled, deinterlaced video stream. A portable DVD player including the digital video enhancer has a generally thin prismatic enclosure having a first major surface, a second major surface separated from said first major surface, and side surfaces connecting the first major surface to the second major surface. At least a portion of the first major surface includes a video display, and the enclosure includes a DVD entry port such that a DVD can be inserted into the enclosure.
摘要翻译：数字图像增强器包括接收隔行视频流的去隔行处理器。去隔行处理器包括第一解交错器和第二解交错器，并且提供去隔行视频流。数字图像增强器还包括接收去隔行视频流的输出的视频输出处理器，以提供缩放的去隔行视频流。包括数字视频增强器的便携式DVD播放器具有大致薄的棱形外壳，其具有第一主表面，与所述第一主表面分离的第二主表面以及将第一主表面连接到第二主表面的侧表面。第一主表面的至少一部分包括视频显示器，并且外壳包括DVD入口端口，使得DVD可以插入到外壳中。

8. 发明授权

US06587158B1 Method and apparatus for reducing on-chip memory in vertical video processing 有权
标题翻译：用于降低垂直视频处理中的片上存储器的方法和装置
公开(公告)号：US06587158B1
公开(公告)日：2003-07-01
申请号：US09359530
申请日：1999-07-22
申请人： Dale R. Adams , Laurence A. Thompson , Jano D. Banks
发明人： Dale R. Adams , Laurence A. Thompson , Jano D. Banks
IPC分类号： H04N964
CPC分类号： H04N7/012 , G09G2310/0229 , H04N5/14 , H04N5/4401 , H04N5/66 , H04N5/775 , H04N5/85 , H04N7/0112 , H04N9/8042
摘要： A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.
摘要翻译：数字图像处理器包括用于存储光栅扫描数据的输入缓冲器。切片缓冲存储器耦合到输入缓冲器以存储所述光栅扫描数据的垂直切片的一部分。垂直切片由具有耦合到切片缓冲存储器的输入的垂直切片处理器处理。垂直切片处理器将垂直切片重新组合成耦合到垂直切片处理器的输出的输出缓冲器中的经处理的光栅扫描数据。数字图像处理器优选地利用多个顺序处理阶段并且沿着垂直切片的水平轴处理光栅扫描数据。

9. 发明授权

US06380978B1 Digital video system and methods for providing same 有权
公开(公告)号：US06380978B1
公开(公告)日：2002-04-30
申请号：US09167527
申请日：1998-10-06
申请人： Dale R. Adams , Laurence A. Thompson , Jano D. Banks , David C. Buuck , Cheng Hwee Chee
发明人： Dale R. Adams , Laurence A. Thompson , Jano D. Banks , David C. Buuck , Cheng Hwee Chee
IPC分类号： H04N701
CPC分类号： G11B33/10 , G06F1/16 , G06F2200/1631 , G06T3/40 , G06T5/002 , G06T5/20 , G06T2207/10016 , G09G5/39 , G09G5/393 , G09G2310/0229 , G11B33/025 , H04N5/14 , H04N5/147 , H04N5/4401 , H04N5/66 , H04N5/775 , H04N5/85 , H04N7/0112 , H04N7/012 , H04N9/8042
摘要： A digital image enhancer includes a deinterlacing processor receptive to an interlaced video stream. The deinterlacing processor includes a first deinterlacer and a second deinterlacer and provides a deinterlaced video stream. The digital image enhancer also includes a video output processor receptive to the output of the deinterlaced video stream to provide a scaled, deinterlaced video stream. A portable DVD player including the digital video enhancer has a generally thin prismatic enclosure having a first major surface, a second major surface separated from said first major surface, and side surfaces connecting the first major surface to the second major surface. At least a portion of the first major surface includes a video display, and the enclosure includes a DVD entry port such that a DVD can be inserted into the enclosure.

10. 发明授权

US08545035B1 Color-patterned front lights 有权
标题翻译：彩色图案前灯
公开(公告)号：US08545035B1
公开(公告)日：2013-10-01
申请号：US13077638
申请日：2011-03-31
申请人： Julien G. Beguin , Jano D. Banks , Kari Rinko , Ilya D. Rosenberg
发明人： Julien G. Beguin , Jano D. Banks , Kari Rinko , Ilya D. Rosenberg
IPC分类号： F21V8/00 , G09G5/00
CPC分类号： G09G3/3413 , G02B6/0038 , G02B6/0068 , G02B6/0073 , G02B6/0076 , G02B6/0083 , G02F1/133514 , G02F1/133615 , G09G3/344 , G09G2300/0452 , G09G2320/0626 , G09G2320/0666 , G09G2340/0407 , G09G2340/0428 , G09G2360/144
摘要： The color patterned front light (CPFL) may be implemented by shining light through a side of a CPFL panel that is situated adjacent to and in front of a monochromic reflective display (MRD). The CPFL may direct one of red, green, blue, or white light through a rear surface of the panel and onto each of the pixels in the MRD. The pixels may be grouped in blocks, such as n-by-m or n-by-n blocks of pixels. The pixels in the block may be selectively activated by the MRD to either absorb the light or reflect the light shone on the respective pixel. By adjusting the representation of the pixels in the MRD, the block may appear to change color based on the colored light from the CPFL that is reflected outward from the display.
摘要翻译：彩色图案化前光（CPFL）可以通过照射位于邻近于单色反射显示器（MRD）前面的CPFL面板的一侧来实现。 CPFL可以通过面板的后表面和MRD中的每个像素来引导红色，绿色，蓝色或白色光中的一种。像素可以被分组成块，例如n×m或n×n个像素块。可以通过MRD选择性地激活块中的像素以吸收光或反射相应像素上的光照。通过调整MRD中的像素的表示，该块可能看起来基于来自显示器向外反射的来自CPFL的彩色光来改变颜色。

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