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1. 发明授权

US06404782B1 Method and apparatus for signaling over packet-based systems 有权
标题翻译：用于基于分组的系统进行信令的方法和装置
公开(公告)号：US06404782B1
公开(公告)日：2002-06-11
申请号：US09157825
申请日：1998-09-21
申请人： Alan David Berenbaum , Robert Brian Dianda , Hubert Rae McLellan, Jr.
发明人： Alan David Berenbaum , Robert Brian Dianda , Hubert Rae McLellan, Jr.
IPC分类号： H04J312
CPC分类号： H04Q11/0478 , H04L2012/563 , H04L2012/5671
摘要： Signaling information is communicated over an ATM link or other packet-based communication link using packet headers. The information may be, for example, telephony signaling information such as an on-hook/off-hook indicator, a ring/no-ring indicator, or any other type of information used in establishing, maintaining, terminating or otherwise configuring a telephony-based communication. In an illustrative embodiment, a single bit of signaling information is incorporated into a low order bit of a packet type indicator field in a header of an ATM user data cell. This low order bit, which is generally used as an End of Message (EOM) indicator in a cell which is part of a multi-cell message, can be used to transmit the signaling information in packets corresponding to single-cell messages. For example, out-bound telephony signaling information may be received from a telephony device such as a telephone or a computer modem, incorporated into an ATM cell header of a single-cell voice sample message, transmitted over an ATM link, removed from the header in an ATM processing device, and delivered to a public switched telephone network. In-bound telephony signaling information may be received from the public switched telephone network, incorporated into an ATM cell header of a single-cell voice sample message, transmitted over an ATM link, removed from the header in an ATM processing device, and delivered to a telephony device.
摘要翻译：信令信息通过ATM链路或其他基于分组的通信链路使用分组头传送。信息可以是例如电话信令信息，例如挂机/摘机指示符，环/无环指示符或用于建立，维护，终止或以其他方式配置电话呼叫的任何其他类型的信息，基于沟通。在说明性实施例中，信令信息的单个位被合并到ATM用户数据单元的报头中的分组类型指示符字段的低位中。通常在作为多小区消息的一部分的小区中用作消息结束（EOM）指示符的该低阶位可用于在与单小区消息相对应的分组中发送信令信息。例如，外部电话信令信息可以从诸如电话或计算机调制解调器的电话设备接收，该电话设备被并入通过ATM链路传输的单个小区语音样本消息的ATM信元头部，从标题在ATM处理设备中，并被传送到公共交换电话网络。入境电话信令信息可以从公共交换电话网络接收，并入ATM单元信元的ATM信元头部，通过ATM链路传送，从ATM处理设备中的报头移除，并传送到电话设备。

2. 发明授权

US06272144B1 In-band device configuration protocol for ATM transmission convergence devices 失效
标题翻译：用于ATM传输融合设备的带内设备配置协议
公开(公告)号：US06272144B1
公开(公告)日：2001-08-07
申请号：US08939746
申请日：1997-09-29
申请人： Alan David Berenbaum , Alexander Gibson Fraser , Hubert Rae McLellan, Jr.
发明人： Alan David Berenbaum , Alexander Gibson Fraser , Hubert Rae McLellan, Jr.
IPC分类号： H04L1256
CPC分类号： H04L49/3081 , H04L49/255 , H04L2012/5652 , H04Q11/0478
摘要： Line card control in an ATM or other packet-based switch is provided using an in-band device configuration in which control messages from a control processor of the switch are transmitted in one or more cells to a transmission convergence device in a line card. The transmission convergence device filters a stream of cells received in the line card in order to identify cells including control messages directed to the line card. The transmission convergence device then executes one or more commands associated with a given control message. Each control message may be transmitted in a single cell including a header and a payload. A message trailer portion of the payload may include device-specific data which specifies an interpretation of the payload structure. For example, the payload may include a series of commands, each including a read or write opcode, an address, and a data field. Alternatively, the device-specific data may indicate that the payload includes a single read command, with a longer address and a larger data field. The message trailer may also include a CRC field which is compared with a CRC computed for the payload to determine whether the control message should be accepted or rejected, and a pass-through data field which is returned unmodified from the line card as part of an acknowledgment of receipt and execution of the control message.
摘要翻译：使用带内设备配置提供ATM或其他基于分组的交换机中的线路卡控制，其中来自交换机的控制处理器的控制消息在一个或多个小区中发送到线路卡中的传输会聚设备。传输会聚装置对在线卡中接收的小区流进行滤波，以便识别包括指向线路卡的控制消息的小区。然后，传输收敛设备执行与给定控制消息相关联的一个或多个命令。每个控制消息可以在包括报头和有效载荷的单个小区中发送。有效负载的消息尾部分可以包括指定有效负载结构的解释的设备特定数据。例如，有效载荷可以包括一系列命令，每个命令包括读或写操作码，地址和数据字段。或者，设备特定数据可以指示有效载荷包括具有较长地址和较大数据字段的单个读取命令。消息预告还可以包括CRC字段，该CRC字段与针对有效载荷计算的CRC进行比较，以确定控制消息是否应被接受或拒绝;以及直接数据字段，其不被修改从线路卡返回，作为确认接收和执行控制消息。

3. 发明授权

US06714168B2 Furniture piece facilitating wireless local area network access 有权
标题翻译：家具件促进无线局域网接入
公开(公告)号：US06714168B2
公开(公告)日：2004-03-30
申请号：US10196165
申请日：2002-07-17
申请人： Alan David Berenbaum
发明人： Alan David Berenbaum
IPC分类号： H04Q720
CPC分类号： H01Q1/44 , H01Q1/246 , H01Q1/40
摘要： The furniture piece facilitating wireless Local Area Network (LAN) access has a work surface and at least one support supporting the work surface. An antenna is disposed in one of the work surface and the support, and an access point is disposed in one of the work surface and the support.
摘要翻译：促进无线局域网（LAN）访问的家具件具有工作表面和至少一个支撑工作表面的支撑件。天线设置在工作表面和支撑件之一中，并且接入点设置在工作表面和支撑件之一中。

4. 发明授权

US07007153B1 Method and apparatus for allocating functional units in a multithreaded VLIW processor 失效
标题翻译：用于在多线程VLIW处理器中分配功能单元的方法和装置
公开(公告)号：US07007153B1
公开(公告)日：2006-02-28
申请号：US09538670
申请日：2000-03-30
申请人： Alan David Berenbaum , Nevin Heintze , Tor E. Jeremiassen , Stefanos Kaxiras
发明人： Alan David Berenbaum , Nevin Heintze , Tor E. Jeremiassen , Stefanos Kaxiras
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional VLIW architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes a compiler to detect parallelism. The disclosed multithreaded VLIW architecture exploits program parallelism by issuing multiple instructions, in a similar manner to single threaded VLIW processors, from a single program sequencer, and also supports multiple program sequencers, as in simultaneous multithreading. Instructions are allocated to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage just before arguments are dispatched to functional units. The allocate stage determines how to group the instructions together to maximize efficiency, by selecting appropriate instructions and assigning the instructions to the FUs. The criteria for selection are thread priority or resource availability or both. Under the thread priority criteria, different threads can have different priorities. The allocate stage selects and forwards the packets (or instructions from packets) for execution belonging to the thread with the highest priority according to the priority policy implemented. Under the resource availability criteria, a packet (having up to K instructions) can be allocated only if the resources (functional units) required by the packet are available for the next cycle. Functional units report their availability to the allocate stage.
摘要翻译：公开了用于在多线程超大指令字（VLIW）处理器中分配功能单元的方法和装置。本发明结合了常规VLIW架构和常规多线程体系结构的技术，以减少单个程序内的执行时间，以及跨工作负载。本发明利用编译器来检测并行性。所公开的多线程VLIW架构通过从单个程序定序器以类似于单线程VLIW处理器的方式发出多个指令来利用程序并行性，并且还支持多个程序定序器，如同时多线程。指令分配给功能单元，以在同一周期内向多个功能单元发出多个VLIW指令。本发明的分配机制在将参数分派到功能单元之前占据了流水线阶段。分配阶段通过选择适当的指令并将指令分配给FU来确定如何将指令组合在一起以最大化效率。选择的标准是线程优先级或资源可用性或两者。在线程优先级标准下，不同的线程可以有不同的优先级。分配阶段根据实现的优先级策略，选择并转发属于具有最高优先级的线程的数据包（或数据包的指令）。在资源可用性标准下，仅当分组所需的资源（功能单元）可用于下一个周期时，才能分配（具有高达K个指令）的分组。功能单位向分配阶段报告其可用性。

5. 发明授权

US06665791B1 Method and apparatus for releasing functional units in a multithreaded VLIW processor 有权
标题翻译：用于释放多线程VLIW处理器中的功能单元的方法和装置
公开(公告)号：US06665791B1
公开(公告)日：2003-12-16
申请号：US09538669
申请日：2000-03-30
申请人： Alan David Berenbaum , Nevin Heintze , Tor E. Jeremiassen , Stefanos Kaxiras
发明人： Alan David Berenbaum , Nevin Heintze , Tor E. Jeremiassen , Stefanos Kaxiras
IPC分类号： G06F15163
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A method and apparatus are disclosed for releasing functional units in a multithreaded very large instruction word (VLIW) processor. The functional unit release mechanism can retrieve the capacity lost due to multiple cycle instructions. The functional unit release mechanism of the present invention permits idle functional units to be reallocated to other threads, thereby improving workload efficiency. Instruction packets are assigned to functional units, which can maintain their state, independent of the issue logic. Each functional unit has an associated state machine (SM) that keeps track of the number of cycles that the functional unit will be occupied by a multiple-cycle instruction. Functional units do not reassign themselves as long as the functional unit is busy. When the instruction is complete, the functional unit can participate in functional unit allocation, even if other functional units assigned to the same thread are still busy. The functional unit release approach of the present invention allows the functional units that are not associated with a multiple-cycle instruction to be allocated to other threads while the blocked thread is waiting, thereby improving throughput of the multithreaded VLIW processor. Since the state is associated with each functional unit separately from the instruction issue unit, the functional units can be assigned to threads independently of the state of any one thread and its constituent instructions.
摘要翻译：公开了用于释放多线程超大指令字（VLIW）处理器中的功能单元的方法和装置。功能单元释放机构可以检索由于多个循环指令而导致的容量损失。本发明的功能单元释放机构允许将空闲功能单元重新分配给其他线程，从而提高工作效率。指令包被分配给功能单元，它们可以保持其状态，而与发行逻辑无关。每个功能单元具有关联的状态机（SM），其跟踪功能单元将被多周期指令占用的周期数。只要功能单元繁忙，功能单元就不会自动重新分配。指令完成后，即使分配给同一线程的其他功能单元仍然忙，功能单元也可以参与功能单元分配。本发明的功能单元释放方法允许在阻塞的线程等待时将不与多周期指令相关联的功能单元分配给其他线程，从而提高多线程VLIW处理器的吞吐量。由于状态与指令发布单元分开地与每个功能单元相关联，所以功能单元可以独立于任何一个线程的状态及其组成指令分配给线程。

6. 发明授权

US5778435A History-based prefetch cache including a time queue 失效
标题翻译：基于历史的预取缓存包括时间队列
公开(公告)号：US5778435A
公开(公告)日：1998-07-07
申请号：US655590
申请日：1996-05-30
申请人： Alan David Berenbaum , Tor E. Jeremiassen
发明人： Alan David Berenbaum , Tor E. Jeremiassen
IPC分类号： G06F9/38 , G06F12/08 , G06F9/00
CPC分类号： G06F9/3806 , G06F12/0862 , G06F9/3814 , G06F9/383 , G06F9/3832 , G06F2212/6024
摘要： A history-based prefetch cache which includes a time queue. The time queue correlates past events with cache misses in a microprocessor. The time queue is set to N cycles, N being a predetermined, arbitrary or programmable amount. The prefetch cache is a prefetch target buffer which receives inputs from a time queue and a cache and determines if an event is present in the cache. If an address is not present in the cache it is prefetched based on past events and inserted into the prefetch target buffer so that the microprocessor will not miss it the next time.
摘要翻译：包含时间队列的基于历史的预取缓存。时间队列将过去的事件与微处理器中的高速缓存未命中相关联。时间队列被设置为N个周期，N是预定的，任意的或可编程的量。预取缓存是从时间队列和高速缓存接收输入并确定高速缓存中是否存在事件的预取目标缓冲区。如果缓存中不存在地址，则根据过去的事件进行预取，并将其插入预取目标缓冲区，以便微处理器下一次不会错过。

7. 发明授权

US07096343B1 Method and apparatus for splitting packets in multithreaded VLIW processor 有权
标题翻译：用于在多线程VLIW处理器中分组数据包的方法和装置
公开(公告)号：US07096343B1
公开(公告)日：2006-08-22
申请号：US09538755
申请日：2000-03-30
申请人： Alan David Berenbaum , Nevin Heintze , Tor E. Jeremiassen , Stefanos Kaxiras
发明人： Alan David Berenbaum , Nevin Heintze , Tor E. Jeremiassen , Stefanos Kaxiras
IPC分类号： G06F9/50
CPC分类号： G06F9/3853 , G06F9/3851 , G06F9/3885
摘要： A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time. Those instructions that cannot be allocated to a functional unit are retained in a ready-to-run register. On subsequent cycles, instruction packets in which all instructions have been issued to functional units are updated from their thread's instruction stream, while instruction packets with instructions that have been held are retained. The functional unit allocation logic can then assign instructions from the newly-loaded instruction packets as well as instructions that were not issued from the retained instruction packets.
摘要翻译：公开了用于在多线程超大指令字（VLIW）处理器中分配功能单元的方法和装置。本发明结合了传统的非常长的指令字架构和传统的多线程体系结构的技术，以减少单个程序内的执行时间以及跨工作负载。本发明利用指令分组分解来恢复传统多线程体系结构损失的一些效率。指令包分割允许在一个周期内部分地发出指令包，在后续周期中发出捆绑的剩余部分。分配硬件分配来自每个分组的指令将适合可用的功能单元，而不是一次分配指令分组中的所有指令。那些不能分配给功能单元的指令被保留在一个准备运行的寄存器中。在随后的周期中，已经从其线程的指令流更新了向功能单元发出了所有指令的指令包，同时保留了具有指令的指令包。然后，功能单元分配逻辑可以从新加载的指令分组以及未从保留的指令分组发出的指令分配指令。

8. 发明授权

US06658551B1 Method and apparatus for identifying splittable packets in a multithreaded VLIW processor 有权
标题翻译：用于在多线程VLIW处理器中识别可分页分组的方法和装置
公开(公告)号：US06658551B1
公开(公告)日：2003-12-02
申请号：US09538757
申请日：2000-03-30
申请人： Alan David Berenbaum , Nevin Heintze , Tor E. Jeremiassen , Stefanos Kaxiras
发明人： Alan David Berenbaum , Nevin Heintze , Tor E. Jeremiassen , Stefanos Kaxiras
IPC分类号： G06F900
CPC分类号： G06F9/3885 , G06F9/3851 , G06F9/3853
摘要： A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word (VLIW) architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. There are times, however, when instruction packets cannot be split without violating the semantics of the instruction packet assembled by the compiler. A packet split identification bit is disclosed that allows hardware to efficiently determine when it is permissible to split an instruction packet. The split bit informs the hardware when splitting is prohibited. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time, provided the split bit has not been set. Those instructions that cannot be allocated to a functional units are retained in a ready-to-run register. On subsequent cycles, instruction packets in which all instructions have been issued to functional units are updated from their thread's instruction stream, while instruction packets with instructions that have been held are retained. The functional unit allocation logic can then assign instructions from the newly-loaded instruction packets as well as instructions that were not issued from the retained instruction packets.
摘要翻译：公开了用于在多线程超大指令字（VLIW）处理器中分配功能单元的方法和装置。本发明结合了传统的非常长的指令字（VLIW）架构和常规多线程体系结构的技术，以减少单个程序内的执行时间，以及跨工作负载。本发明利用指令分组分解来恢复传统多线程体系结构损失的一些效率。指令包分割允许在一个周期内部分地发出指令包，在后续周期中发出捆绑的剩余部分。然而，有时候，当指令包不能被分割而不违反编译器组装的指令包的语义时，公开了一种分组分割识别位，其允许硬件有效地确定何时可以分割指令分组。拆分时禁止拆分硬件。分配硬件分配来自每个分组的指令将适合可用的功能单元，而不是一次分配指令分组中的所有指令，前提是分裂位尚未设置。那些不能分配给功能单元的指令将保留在一个即可运行的寄存器中。在随后的周期中，已经从其线程的指令流更新了向功能单元发出了所有指令的指令包，同时保留了具有指令的指令包。然后，功能单元分配逻辑可以从新加载的指令分组以及未从保留的指令分组发出的指令分配指令。

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