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    • 7. 发明授权
    • Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data
    • 时钟数据恢复(“CDR”)电路,可变频率数据的装置和方法
    • US08130891B2
    • 2012-03-06
    • US12710250
    • 2010-02-22
    • Dennis KimJason WeiYohan FransTodd BystromNhat NguyenKevin Donnelly
    • Dennis KimJason WeiYohan FransTodd BystromNhat NguyenKevin Donnelly
    • H03D3/24
    • H03L7/0814H03L7/091H04L7/0331
    • A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.
    • 诸如CDR电路的电路包括采样器,以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中,时钟电路包括耦合到第一,第二和第三级的失调逻辑,并且能够响应于第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中,指示器检测可变数据比特率,并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中,时钟电路包括失速逻辑,指示器和计数器。 在本发明的第五实施例中,时钟电路包括平均电路,用于响应于在预定时间段内的第一和第二调整信号的平均来输出相位调整信号。
    • 8. 发明授权
    • Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data
    • 时钟数据恢复(“CDR”)电路,可变频率数据的装置和方法
    • US07668271B2
    • 2010-02-23
    • US10675027
    • 2003-09-30
    • Dennis KimJason WeiYohan FransTodd BystromNhat NguyenKevin Donnelly
    • Dennis KimJason WeiYohan FransTodd BystromNhat NguyenKevin Donnelly
    • H04L7/00
    • H03L7/0814H03L7/091H04L7/0331
    • A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.
    • 诸如CDR电路的电路包括采样器,以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。 时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。 在本发明的第二实施例中,该电路包括一个与第一,第二和第三级耦合的稳态逻辑,并能够响应第一和第二级输出信号保持相位调整信号。 在本发明的第三实施例中,指示器检测可变数据比特率,并且计数器为调整信号提供可选择的相位调整步长。 在本发明的第四实施例中,电路包括停顿逻辑,指示器和计数器。 在本发明的第五实施例中,电路包括平均电路,用于响应于在预定时间段内对第一和第二调整信号的平均来输出相位调整信号。