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1. 发明申请

US20080196032A1 HARDWARE DEVICE FOR PROCESSING THE TASKS OF AN ALGORITHM IN PARALLEL 失效
标题翻译：用于处理并行算法的任务的硬件设备
公开(公告)号：US20080196032A1
公开(公告)日：2008-08-14
申请号：US12109001
申请日：2008-04-24
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作

2. 发明授权

US06219416B1 Method and apparatus for processing FISU frames according to the Signalling System 7 protocol 失效
标题翻译：根据信令系统7协议处理FISU帧的方法和装置
公开(公告)号：US06219416B1
公开(公告)日：2001-04-17
申请号：US08807491
申请日：1997-02-27
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： H04M1500
CPC分类号： H04Q3/0025 , H04Q2213/13003 , H04Q2213/13103 , H04Q2213/13174 , H04Q2213/13176 , H04Q2213/13216 , H04Q2213/13305 , H04Q2213/1332 , H04Q2213/13322
摘要： A FISU frame handler which is connected between an adapter and a SS7 low speed network. For each FISU frames transmitted or received in the adapter, an interrupt is generated to a processor located in the adapter. In order to diminish the number of processor interruptions, the FISU frames are externally processed by the FISU frame handler by discarding repeated FISU frames transmitted from the network so as to generate idle state signals to the adapter and by converting idle state signals received from the adapter into repetitive FISU frames to transmit them to the network without interrupting the processor. In order to perform both functions, the FISU frame handler comprises two dedicated hardware units which operate according to specific methods.
摘要翻译：连接在适配器和SS7低速网络之间的FISU帧处理器。对于在适配器中发送或接收的每个FISU帧，将向位于适配器中的处理器生成中断。为了减少处理器中断次数，FISU帧由FISU帧处理器通过丢弃从网络发送的重复的FISU帧来进行外部处理，以便向适配器产生空闲状态信号，并通过转换从适配器接收的空闲状态信号重复的FISU帧将其发送到网络而不中断处理器。为了执行这两个功能，FISU帧处理器包括根据特定方法操作的两个专用硬件单元。

3. 发明授权

US06999994B1 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US06999994B1
公开(公告)日：2006-02-14
申请号：US09606899
申请日：2000-06-29
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F15/16 , G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units.
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作。

4. 发明授权

US06961337B2 Interleaved processing system for processing frames within a network router 失效
标题翻译：用于处理网络路由器内的帧的交织处理系统
公开(公告)号：US06961337B2
公开(公告)日：2005-11-01
申请号：US09753921
申请日：2001-01-03
申请人： Jean Francois Le Pennec , Claude Pin , Alain Benayoun , Patrick Michel
发明人： Jean Francois Le Pennec , Claude Pin , Alain Benayoun , Patrick Michel
IPC分类号： H04L12/701 , H04L12/741 , H04L12/773 , H04L12/28
CPC分类号： H04L45/60 , H04L45/00 , H04L45/54 , Y10S707/99933
摘要： A system and method for performing interleaved packet processing. A packet includes a source address bit pattern and a destination address bit pattern that are processed by a task processor in accordance with a data tree. A first bank of registers is utilized to load an instruction to be executed by the task processor at nodes of the data tree in accordance with the source address bit pattern. A second bank of registers is utilized for loading an instruction to be executed by the task processor at nodes of the data tree in accordance with the destination address bit pattern. A task scheduler enables the first bank of registers to transfer an instruction loaded therein for processing by the task processor only during even time cycles and for enabling the second bank of registers to transfer an instruction loaded therein for processing by the task processor only during odd time cycles.
摘要翻译：一种用于执行交织分组处理的系统和方法。分组包括根据数据树由任务处理器处理的源地址位模式和目的地地址位模式。根据源地址位模式，第一组寄存器被用来加载任务处理器在数据树的节点执行的指令。第二组寄存器用于根据目的地地址位模式将在任务处理器执行的指令加载到数据树的节点处。任务调度器使得第一组寄存器仅在偶数时间周期期间传送加载在其中以供任务处理器处理的指令，并且仅允许第二组寄存器在奇数时间内传送其中加载的指令以供任务处理器处理周期。

5. 发明授权

US06675291B1 Hardware device for parallel processing of any instruction within a set of instructions 有权
标题翻译：用于并行处理一组指令内的任何指令的硬件设备
公开(公告)号：US06675291B1
公开(公告)日：2004-01-06
申请号：US09558792
申请日：2000-04-26
申请人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
IPC分类号： G06F944
CPC分类号： G06F9/38 , G06F9/30145 , G06F9/3822
摘要： Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means (22-30) for activating the processing of one or several processes (32-38) determined by the operand fields of the instruction, decision macroblocks (12-20) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.
摘要翻译：用于并行处理具有定义操作数字段和其他数据字段的相同格式的一组指令的确定指令的硬件设备，该确定的指令的执行被表示为包括多个处理的算法，其根据决定进行处理。这种设备包括用于激活由指令的操作数字段确定的一个或几个处理（32-38）的处理的装置（22-30），每个与组的特定指令相关联的决策宏块（12-20）的指令，所确定的指令仅选择一个决策marcoblock，以便确定哪些是要激活的进程来执行所确定的指令。

6. 发明授权

US08190862B2 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US08190862B2
公开(公告)日：2012-05-29
申请号：US12109001
申请日：2008-04-24
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9/30 , G06F9/46 , G06F9/54
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units.
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作。

7. 发明申请

US20060112393A1 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US20060112393A1
公开(公告)日：2006-05-25
申请号：US11322378
申请日：2006-01-03
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作

8. 发明授权

US06516319B1 Parallelized processing device for processing search keys based upon tree structure 失效
标题翻译：基于树结构处理搜索键的并行处理设备
公开(公告)号：US06516319B1
公开(公告)日：2003-02-04
申请号：US09569493
申请日：2000-05-11
申请人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Claude Pin , Patrick Michel
IPC分类号： G06F1730
CPC分类号： G06F17/30961 , G06F17/3061 , G06F17/30952 , Y10S707/99933
摘要： A device for parallel processing of subtrees within a binary tree for searching for the tree leaf matching a search key. The search is performed at each node by applying a recursive function associated with each node and whose parameters depend on the node for determining which branch, left or right, is to be taken in accordance with the search key. The device includes subtree register blocks for storing the recursive functions, processors for processing the recursive functions, a control unit that assigns one processor to the processing of the recursive functions contained in a block that sent the request to the control unit, and means for selecting subtrees included in the sequence of branches between the root and the leaf defined in accordance with the search key in response to the processing of blocks.
摘要翻译：用于并行处理二进制树中的子树的装置，用于搜索与搜索关键字匹配的树叶。通过应用与每个节点相关联的递归函数并且其参数依赖于该节点来确定将根据搜索关键字被采取左侧或右侧的哪个分支来在每个节点处执行搜索。该装置包括用于存储递归函数的子树寄存器块，用于处理递归函数的处理器，将包含在向控制单元发送请求的块中的递归函数的处理分配给一个处理器的控制单元，以及用于选择子树包括在响应于块的处理的根据搜索关键字定义的根和叶之间的分支序列中。

9. 发明授权

US06401188B1 Method for selection on a pattern sequence 有权
标题翻译：在图案序列上选择的方法
公开(公告)号：US06401188B1
公开(公告)日：2002-06-04
申请号：US09245189
申请日：1999-02-05
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F1202
CPC分类号： H04M15/8044 , H04M15/00 , H04M2215/42 , H04M2215/745
摘要： A method is disclosed for making a selection on a pattern sequence depending on whether or not the sequence belongs to a routing set, the routing set having at least two keys. The selection is made in a single step by analyzing a selection word (CASE SELECT) identifying the routing set.
摘要翻译：公开了一种用于根据序列是否属于路由集合对模式序列进行选择的方法，该路由集具有至少两个密钥。通过分析识别路由集的选择字（CASE SELECT），在单个步骤中进行选择。

10. 发明授权

US08635620B2 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US08635620B2
公开(公告)日：2014-01-21
申请号：US13365360
申请日：2012-02-03
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9/46 , G06F15/76 , G06F7/38
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units.
摘要翻译：一种硬件设备，用于同时处理与包括多个进程的算法相关联的一组固定的预定任务，其中一些进程取决于二进制决策，包括用于处理数据，作出决定和/或处理数据的多个任务单元并作出决定，包括源任务单位和目标任务单位。任务互连逻辑意味着将任务单元互连以将来自源任务单元的动作传送到目的地任务单元。每个任务单元包括处理器，用于响应于接收到的请求动作仅执行与算法相关联的固定的一组预定任务的特定单个任务，以及状态管理器，用于处理源任务单元的动作并构建要发送到目标任务单元的动作。

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