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1. 发明申请

US20090096543A1 MULTI-FORMAT ALL-DIGITAL MODULATOR AND METHOD 有权
标题翻译：多格式全数字调制器和方法
公开(公告)号：US20090096543A1
公开(公告)日：2009-04-16
申请号：US12027692
申请日：2008-02-07
申请人： Alaa El-Agha , Dustin Griesdorf , Gareth P. Weale , Jakob Nielson
发明人： Alaa El-Agha , Dustin Griesdorf , Gareth P. Weale , Jakob Nielson
IPC分类号： H04L27/12
CPC分类号： H04L27/10 , H04L27/12
摘要： A method, system and digital modulator for modulation are provided The modulator includes a dividing mechanism for dividing a reference clock by a divide value to produce a modulated signal associated with at least one input data, and a control unit for providing at least one divide sequence to the dividing mechanism. The at least one divide sequence includes a sequence of one or more divide values. The divide value of the divide sequence is configurable and selectively provided to the dividing mechanism based on the at least one input data. The method includes configuring at least one divide sequence including a sequence of one or more divide values, and selecting a divide value from the at least one divide sequence based on at least one input data. The method includes dividing a reference clock by the selected divide value and generating a modulated signal based on the divide operation. The system for modulation-based commutations link includes a modulation unit having a dividing mechanism for dividing a reference clock by a divide value, and a configuration register for one or more configurable divide sequences.
摘要翻译：提供了用于调制的方法，系统和数字调制器。调制器包括分频机构，用于将参考时钟除以除法值，以产生与至少一个输入数据相关联的调制信号;以及控制单元，用于提供至少一个除法序列到分割机制。所述至少一个除法序列包括一个或多个除法值的序列。基于所述至少一个输入数据，所述除法序列的除法值可配置并选择性地提供给所述分割机构。所述方法包括配置包括一个或多个除法值的序列的至少一个除法序列，以及基于至少一个输入数据从所述至少一个除法序列中选择除法值。该方法包括将参考时钟除以所选择的除法值，并根据除法运算产生调制信号。用于基于调制的交换链路的系统包括具有用于将参考时钟除以除法的分频机制的调制单元和用于一个或多个可配置分频序列的配置寄存器。

2. 发明授权

US07816979B2 Configurable demodulator and demodulation method 有权
标题翻译：可配置解调和解调方式
公开(公告)号：US07816979B2
公开(公告)日：2010-10-19
申请号：US12028292
申请日：2008-02-08
申请人： Alaa El-Agha , Dustin Griesdorf , Gareth P. Weale , Jakob Nielson
发明人： Alaa El-Agha , Dustin Griesdorf , Gareth P. Weale , Jakob Nielson
IPC分类号： H04L27/14
CPC分类号： H04L27/10 , H03D3/006 , H04L27/156 , H04L27/1563
摘要： A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison.
摘要翻译：提供了一种用于频移键解调的方法和系统。该系统包括用于对由调制信号定义的窗口内的参考时钟进行计数的计数块，用于将来自计数块的计数值与数字多电平阈值进行比较的检测器，以及基于比较输出基带数据的配置用于配置计数块和检测器中的至少一个的块。该方法包括对由FSK调制信号定义的窗口内的参考时钟进行计数，并作为计数结果输出计数值，并根据比较将计数值与多电平阈值进行比较以输出基带数据。

3. 发明申请

US20090097588A1 DIGITAL DATA ENCODING AND DECODING METHOD AND SYSTEM 有权
标题翻译：数字编码和解码方法与系统
公开(公告)号：US20090097588A1
公开(公告)日：2009-04-16
申请号：US12027703
申请日：2008-02-07
申请人： Alaa El-Agha , Dustin Griesdorf
发明人： Alaa El-Agha , Dustin Griesdorf
IPC分类号： H04L27/00
CPC分类号： H04J3/0602 , H04L7/041 , H04L25/4904 , H04L25/493
摘要： Digital data encoding and decoding method and system is provided. The method for digital data communication include encoding bit stream having monitoring a specific bit pattern in the bit stream when a frame signal is received, and based on the monitoring, creating a unique encoding pattern for the frame signal in encoded data. The system for digital data communication includes an encoder having a control unit for monitoring incoming bit stream to detect a specific bit pattern at a bit position relative to a frame signal and asserting a control signal, and a mark and space unit for generating encoded data having at least one of one or more marks and one or more spaces, based on the bit stream in response to the control signal so that the frame signal is embedded into the encoded data. The method for decoding includes recovering bit stream from encoded data. The encoded data is generated using a unique encoding pattern for a frame signal in the encoded data. The recovering includes detecting at least one of mark and space. The method includes recovering a frame signal from the encoded data, including detecting a pattern associated with the unique encoding pattern based on the detection of the at least one of mark and space. The system for decoding includes a first recover for recovering bit stream from encoded data. The encoded data is generated using a unique encoding pattern for a frame signal in the encoded data. The first recover includes a circuit for detecting at least one of mark and space. The system includes a second recover for recovering a frame signal from the encoded data. The second recover includes a circuit for detecting a pattern associated with the unique encoding pattern based on the detection of the at least one of mark and space.
摘要翻译：提供数字数据编码和解码方法和系统。用于数字数据通信的方法包括：当接收到帧信号时，具有在比特流中监视特定位模式的编码位流，并且基于监视，为编码数据中的帧信号创建唯一的编码模式。用于数字数据通信的系统包括：编码器，具有控制单元，用于监视输入位流，以相对于帧信号在位位置检测特定位模式，并且断言控制信号;以及标记和空间单元，用于产生具有基于比特流响应于控制信号，使一个或多个标记和一个或多个空格中的至少一个标记和一个或多个空格，使得帧信号被嵌入到编码数据中。解码方法包括从编码数据中恢复比特流。使用用于编码数据中的帧信号的唯一编码模式来生成编码数据。恢复包括检测标记和空间中的至少一个。该方法包括从编码数据中恢复帧信号，包括基于对标记和空间中的至少一个的检测来检测与唯一编码模式相关联的模式。用于解码的系统包括用于从编码数据中恢复比特流的第一恢复。使用用于编码数据中的帧信号的唯一编码模式来生成编码数据。第一恢复包括用于检测标记和空间中的至少一个的电路。该系统包括用于从编码数据中恢复帧信号的第二恢复。第二恢复包括用于基于对标记和空间中的至少一个的检测来检测与唯一编码模式相关联的模式的电路。

4. 发明授权

US08144802B2 Digital data encoding and decoding method and system 有权
标题翻译：数字数据编解码方法及系统
公开(公告)号：US08144802B2
公开(公告)日：2012-03-27
申请号：US12027703
申请日：2008-02-07
申请人： Alaa El-Agha , Dustin Griesdorf
发明人： Alaa El-Agha , Dustin Griesdorf
IPC分类号： H04L27/10 , H04L7/02 , H04B14/04 , H03M5/14 , H04M7/12
CPC分类号： H04J3/0602 , H04L7/041 , H04L25/4904 , H04L25/493
摘要： Digital data encoding and decoding method and system is provided. The data encoding includes encoding a frame signal into a bit stream, including detecting a specific bit pattern in the bit stream when the frame signal is present, generating a control signal in respect to the specific bit pattern, and encoding the bit stream into one or more marks and one or more spaces so that encoded data include a unique encoding pattern for the frame signal. The data decoding includes detecting at least one of mark and space from encoded data, recovering a bit stream from the encoded data when the at least one of mark and space is present, detecting a specific bit pattern associating with a frame signal from the encoded data when the at least one of mark and space is present, and recovering the frame signal from the encoded data.
摘要翻译：提供数字数据编码和解码方法和系统。数据编码包括将帧信号编码为比特流，包括当存在帧信号时检测比特流中的特定比特模式，生成关于特定比特码型的控制信号，并将比特流编码为一个或更多的标记和一个或多个空格，使得编码数据包括用于帧信号的唯一编码模式。数据解码包括从编码数据中检测标记和空间中的至少一个，当存在标记和空格的至少一个时从编码数据中恢复比特流，检测与来自编码数据的帧信号相关联的特定位模式当存在标记和空格中的至少一个时，并且从编码数据中恢复帧信号。

5. 发明授权

US07795986B2 Multi-format all-digital modulator and method 有权
标题翻译：多格式全数字调制器和方法
公开(公告)号：US07795986B2
公开(公告)日：2010-09-14
申请号：US12027692
申请日：2008-02-07
申请人： Alaa El-Agha , Dustin Griesdorf , Gareth P. Weale , Jakob Nielson
发明人： Alaa El-Agha , Dustin Griesdorf , Gareth P. Weale , Jakob Nielson
IPC分类号： H03C3/00 , H03K7/06 , H04L27/12
CPC分类号： H04L27/10 , H04L27/12
摘要： A method, system and digital modulator for modulation are provided The modulator includes a dividing mechanism for dividing a reference clock by a divide value to produce a modulated signal associated with at least one input data, and a control unit for providing at least one divide sequence to the dividing mechanism. The at least one divide sequence includes a sequence of one or more divide values. The divide value of the divide sequence is configurable and selectively provided to the dividing mechanism based on the at least one input data. The method includes configuring at least one divide sequence including a sequence of one or more divide values, and selecting a divide value from the at least one divide sequence based on at least one input data. The method includes dividing a reference clock by the selected divide value and generating a modulated signal based on the divide operation. The system for modulation-based commutations link includes a modulation unit having a dividing mechanism for dividing a reference clock by a divide value, and a configuration register for one or more configurable divide sequences.
摘要翻译：提供了用于调制的方法，系统和数字调制器。调制器包括分频机构，用于将参考时钟除以除法值，以产生与至少一个输入数据相关联的调制信号;以及控制单元，用于提供至少一个除法序列到分割机制。所述至少一个除法序列包括一个或多个除法值的序列。基于所述至少一个输入数据，所述除法序列的除法值可配置并选择性地提供给所述分割机构。所述方法包括配置包括一个或多个除法值的序列的至少一个除法序列，以及基于至少一个输入数据从所述至少一个除法序列中选择除法值。该方法包括将参考时钟除以所选择的除法值，并根据除法运算产生调制信号。用于基于调制的交换链路的系统包括具有用于将参考时钟除以除法的分频机制的调制单元和用于一个或多个可配置分频序列的配置寄存器。

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