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1. 发明授权

US08001592B2 Methods and apparatus for accessing resources using a multiprocessor in a trusted mode 有权
标题翻译：在可信模式下使用多处理器访问资源的方法和装置
公开(公告)号：US08001592B2
公开(公告)日：2011-08-16
申请号：US11746338
申请日：2007-05-09
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： G06F21/00 , G06F12/14
CPC分类号： G06F21/79 , G06F12/1491 , G06F21/74 , G06F2221/2105 , G06F2221/2149 , H04L9/3226
摘要： A system and method are disclosed which may include entering a secure mode by a processor, whereby the processor may initiate a transfer of information into or out of the processor, but no external device may initiate a transfer of information into or out of the processor; sending a DMA (direct memory access) command including at least one authorization code from the processor to at least one trusted data storage region external to the processor; evaluating the authorization code; and enabling the processor to access at least one trusted data storage location within the trusted data storage region if the authorization code is valid.
摘要翻译：公开了一种系统和方法，其可以包括由处理器进入安全模式，由此处理器可以发起信息进入或离开处理器的传输，但是没有外部设备可以发起信息传入或传出处理器; 将包括至少一个授权码的DMA（直接存储器访问）命令从处理器发送到处理器外部的至少一个可信数据存储区域; 评估授权码; 以及如果所述授权码有效，则使所述处理器能够访问所述可信数据存储区域内的至少一个可信数据存储位置。

2. 发明授权

US07958371B2 Methods and apparatus for secure operating system distribution in a multiprocessor system 有权
标题翻译：用于多处理器系统中安全操作系统分发的方法和装置
公开(公告)号：US07958371B2
公开(公告)日：2011-06-07
申请号：US11746416
申请日：2007-05-09
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： G06F12/14
CPC分类号： G06F21/57
摘要： Methods and apparatus provide for: decrypting a first of a plurality of operating systems (OSs) within a first processor of a multiprocessing system using a private key thereof, the plurality of OSs having been encrypted by a trusted third party, other than a manufacturer of the multiprocessing system, using respective public keys, each paired with the private key; executing an authentication program using the first processor to verify that the first OS is valid; and executing the first OS on the first processor.
摘要翻译：方法和装置提供：使用其私钥对多处理系统的第一处理器内的多个操作系统（OS）中的第一个进行解密，所述多个操作系统已被可信赖的第三方加密，多处理系统，使用相应的公钥，每个与私钥配对; 使用所述第一处理器执行认证程序以验证所述第一OS是否有效; 以及在所述第一处理器上执行所述第一OS。

3. 发明授权

US07627740B2 Methods and apparatus for dynamic prediction by software 有权
标题翻译：软件动态预测方法与装置
公开(公告)号：US07627740B2
公开(公告)日：2009-12-01
申请号：US11344403
申请日：2006-01-31
申请人： Masahiro Yasue , Akiyuki Hatakeyama
发明人： Masahiro Yasue , Akiyuki Hatakeyama
IPC分类号： G06F9/312
CPC分类号： G06F9/3846 , G06F9/30047 , G06F9/30072 , G06F9/3804
摘要： A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.
摘要翻译：一种用于指定与用于实现分支操作的分支指令相关联的条件预取指令的第一部分中的值的方法，存储介质，处理器指令和处理器，在指令的第二部分中指定目标指令地址提供该值，以确定是否满足条件，并且在满足条件时将从目标指令地址开始的一个或多个指令预取到处理器的指令缓冲器中。

4. 发明申请

US20080282063A1 METHODS AND APPARATUS FOR LATENCY CONTROL IN A MULTIPROCESSOR SYSTEM 有权
标题翻译：多处理器系统中的时间控制的方法和装置
公开(公告)号：US20080282063A1
公开(公告)日：2008-11-13
申请号：US11746408
申请日：2007-05-09
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： G06F15/00 , G06F13/00
CPC分类号： G06F13/387
摘要： Methods and apparatus provide for a multiprocessor system including: a plurality of sub-processors operatively coupled to one another over a ring bus, whereby data may be transmitted over one or more paths on the ring bus between pairs of the sub-processors; and a plurality of programmable delay circuits, each associated with at least one of the sub-processors, and each being operable to alter a delay of data transfer at least one of into and out of its associated sub-processor in order to alter one or more latencies associated with the paths on the ring bus between pairs of the sub-processors.
摘要翻译：方法和装置提供一种多处理器系统，其包括：通过环形总线可操作地彼此耦合的多个子处理器，由此数据可以在子处理器对之间的环形总线上的一个或多个路径上传输; 以及多个可编程延迟电路，每个都与子处理器中的至少一个相关联，并且每个子程序可操作以改变数据传输的延迟，其中至少一个进入和移出其相关联的子处理器，以便改变一个或多个与子处理器对之间的环形总线上的路径相关联的更多延迟。

5. 发明申请

US20060190733A1 Methods and apparatus for resource management in a processor 审中-公开
标题翻译：处理器中资源管理的方法和装置
公开(公告)号：US20060190733A1
公开(公告)日：2006-08-24
申请号：US11347618
申请日：2006-02-03
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： H04L9/00
CPC分类号： G06F21/53 , A63F13/12 , A63F13/71 , A63F2300/532 , A63F2300/5586 , G06F21/10 , G06F21/51 , G06Q20/123
摘要： Methods and apparatus provide for receiving encrypted content including program code, data, and a digital signature in a memory of a processing system, the content being encrypted using a first key; decrypting the encrypted content using a second key stored locally within the processing system; retrieving the digital signature from the content and verifying its authenticity; and permitting use of one or more processing resources that are operable to facilitate the execution of the program code by a processor of the processing system if the digital signature is authentic.
摘要翻译：方法和装置提供在处理系统的存储器中接收包括程序代码，数据和数字签名的加密内容，所述内容使用第一密钥加密; 使用在处理系统内本地存储的第二密钥对加密内容进行解密; 从内容中检索数字签名并验证其真实性; 并且如果数字签名是可信的，则允许使用一个或多个处理资源，所述处理资源可操作以便于处理系统的处理器执行程序代码。

6. 发明授权

US07788467B2 Methods and apparatus for latency control in a multiprocessor system 有权
标题翻译：多处理器系统中等待时间控制的方法和装置
公开(公告)号：US07788467B2
公开(公告)日：2010-08-31
申请号：US11746408
申请日：2007-05-09
申请人： Akiyuki Hatakeyama
发明人： Akiyuki Hatakeyama
IPC分类号： G06F5/06
CPC分类号： G06F13/387
摘要： Methods and apparatus provide for a multiprocessor system including: a plurality of sub-processors operatively coupled to one another over a ring bus, whereby data may be transmitted over one or more paths on the ring bus between pairs of the sub-processors; and a plurality of programmable delay circuits, each associated with at least one of the sub-processors, and each being operable to alter a delay of data transfer at least one of into and out of its associated sub-processor in order to alter one or more latencies associated with the paths on the ring bus between pairs of the sub-processors.
摘要翻译：方法和装置提供一种多处理器系统，其包括：通过环形总线可操作地彼此耦合的多个子处理器，由此数据可以在子处理器对之间的环形总线上的一个或多个路径上传输; 以及多个可编程延迟电路，每个都与子处理器中的至少一个相关联，并且每个子程序可操作以改变数据传输的延迟，其中至少一个进入和移出其相关联的子处理器，以便改变一个或多个与子处理器对之间的环形总线上的路径相关联的更多延迟。

7. 发明授权

US07502928B2 Methods and apparatus for secure data processing and transmission 有权
标题翻译：用于安全数据处理和传输的方法和装置
公开(公告)号：US07502928B2
公开(公告)日：2009-03-10
申请号：US10985354
申请日：2004-11-12
申请人： Masakazu Suzuoki , Akiyuki Hatakeyama
发明人： Masakazu Suzuoki , Akiyuki Hatakeyama
IPC分类号： H04L9/00
CPC分类号： G06F21/72 , G06F21/74
摘要： Methods and apparatus for placing a processing unit into one or more of a plurality of operational modes are disclosed wherein: the apparatus includes a local memory, a bus operable to carry information to and from the local memory, one or more arithmetic processing units operable to process data and operatively coupled to the local memory, and a security circuit operable to place the apparatus into the operational modes; and the plurality of operational modes includes a first mode whereby the apparatus and an external device may initiate a transfer of information into or out of the memory over the bus, a second mode whereby neither the apparatus nor the external device may initiate a transfer of information into or out of the memory over the bus, and a third mode whereby the apparatus may initiate a transfer of information into or out of the memory over the bus, but the external device may not initiate a transfer of information into or out of the memory over the bus.
摘要翻译：公开了一种用于将处理单元置于多个操作模式中的一个或多个操作模式中的方法和装置，其中：所述装置包括本地存储器，可操作以向本地存储器携带信息的总线，一个或多个算术处理单元，处理数据并且可操作地耦合到本地存储器，以及可操作以将设备置于操作模式的安全电路; 并且所述多个操作模式包括第一模式，由此所述装置和外部设备可以通过所述总线发起向所述存储器传送信息;第二模式，其中所述设备和所述外部设备都不可能发起信息的传送通过总线进入或离开存储器，以及第三模式，由此设备可以通过总线发起信息传入或传出存储器，但是外部设备可能不会发起信息传入或传出存储器在公共汽车上。

8. 发明申请

US20070180271A1 Apparatus and method for providing key security in a secure processor 审中-公开
标题翻译：在安全处理器中提供关键安全性的装置和方法
公开(公告)号：US20070180271A1
公开(公告)日：2007-08-02
申请号：US11345848
申请日：2006-02-02
申请人： Akiyuki Hatakeyama , H. Hofstee , Kanna Shimizu
发明人： Akiyuki Hatakeyama , H. Hofstee , Kanna Shimizu
IPC分类号： G06F12/14 , H04L9/00 , H04L9/32 , G06F11/30 , G06F11/00 , G06F1/26 , G08B13/00 , G08B21/00 , G08B29/00
CPC分类号： G06F21/53 , G06F21/72 , G06F2221/2105
摘要： An apparatus and method for providing key security in a secure processor are provided. With the apparatus and method, a two-tiered key security mechanism is provided. On a first tier, a decryption mechanism and a fixed size storage area for a core key are hard-wired into the chip design. It is this first tier that is common to all systems and customers utilizing the processor design. On a second tier, off-chip but within the system is a secondary security key storage device that stores all the keys that are required by the particular system architecture. The off-chip storage device is programmed with the necessary keys before the system is shipped to the customer and thus, provides the needed flexibility. For protection, the keys are stored as an encrypted image using the core key stored on-chip.
摘要翻译：提供了一种用于在安全处理器中提供密钥安全性的装置和方法。通过该装置和方法，提供了一种双层密钥安全机制。在第一层上，用于核心密钥的解密机制和固定大小的存储区域被硬连接到芯片设计中。正是这个第一层是所有系统和客户利用处理器设计的共同之处。在第二层，片外但系统内是存储特定系统架构所需的所有密钥的辅助安全密钥存储设备。片外存储设备在系统发货给客户之前用必要的密钥进行编程，从而提供所需的灵活性。为了保护，使用存储在芯片上的核心密钥将密钥存储为加密图像。

9. 发明申请

US20060212680A1 Methods and apparatus for dynamic prediction by software 有权
公开(公告)号：US20060212680A1
公开(公告)日：2006-09-21
申请号：US11344403
申请日：2006-01-31
申请人： Masahiro Yasue , Akiyuki Hatakeyama
发明人： Masahiro Yasue , Akiyuki Hatakeyama
IPC分类号： G06F9/30
CPC分类号： G06F9/3846 , G06F9/30047 , G06F9/30072 , G06F9/3804
摘要： A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.

10. 发明申请

US20060112213A1 Methods and apparatus for secure data processing and transmission 有权
公开(公告)号：US20060112213A1
公开(公告)日：2006-05-25
申请号：US10985354
申请日：2004-11-12
申请人： Masakazu Suzuoki , Akiyuki Hatakeyama
发明人： Masakazu Suzuoki , Akiyuki Hatakeyama
IPC分类号： G06F12/14
CPC分类号： G06F21/72 , G06F21/74
摘要： Methods and apparatus for placing a processing unit into one or more of a plurality of operational modes are disclosed wherein: the apparatus includes a local memory, a bus operable to carry information to and from the local memory, one or more arithmetic processing units operable to process data and operatively coupled to the local memory, and a security circuit operable to place the apparatus into the operational modes; and the plurality of operational modes includes a first mode whereby the apparatus and an external device may initiate a transfer of information into or out of the memory over the bus, a second mode whereby neither the apparatus nor the external device may initiate a transfer of information into or out of the memory over the bus, and a third mode whereby the apparatus may initiate a transfer of information into or out of the memory over the bus, but the external device may not initiate a transfer of information into or out of the memory over the bus.

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