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1. 发明授权

US5555520A Trench capacitor cells for a dram having single monocrystalline capacitor electrode 失效
标题翻译：用于具有单个单晶电容器电极的电容器的沟槽电容器电池
公开(公告)号：US5555520A
公开(公告)日：1996-09-10
申请号：US353368
申请日：1994-12-02
申请人： Akira Sudo , Yusuke Kohyama , Haruhiko Koyama
发明人： Akira Sudo , Yusuke Kohyama , Haruhiko Koyama
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94 , H01L29/68
CPC分类号： H01L27/10861 , H01L27/10829 , H01L29/945
摘要： The present structure is characterized by the electrode of a trench capacitor of a DRAM and a periphery thereof. A trench is formed adjacent to an N type region in a substrate. An insulating film is formed on the side wall of this trench and only a part of the insulating film around the upper portion of the trench is removed, forming a window. An N type polycrystalline silicon film of a lower capacitor electrode is formed over a region from the bottom of the trench to below the window, and a capacitor insulating film is formed on this polycrystalline silicon film. A polycrystalline silicon film which becomes a first upper capacitor electrode is formed on the capacitor insulating film, filling the trench up to the lower edge of the window. A monocrystalline silicon film which becomes a second upper capacitor electrode is formed on the latter polycrystalline silicon film in such a way as to contact an N type region, filling the upper portion of the trench. An insulating film similar to a gate insulating film on the substrate is formed on the monocrystalline silicon film.
摘要翻译：本结构的特征在于DRAM的沟槽电容器的电极及其周边。在衬底中与N型区域相邻地形成沟槽。在该沟槽的侧壁上形成绝缘膜，并且除去沟槽上部周围的仅绝缘膜的一部分，形成窗口。在从沟槽的底部到窗口的下方的区域上形成下部电容电极的N型多晶硅膜，在该多晶硅膜上形成电容绝缘膜。在电容器绝缘膜上形成成为第一上电容器电极的多晶硅膜，将沟槽填充到窗口的下边缘。在后面的多晶硅膜上形成成为第二上电容器电极的单晶硅膜，以接触填充沟槽上部的N型区域。在单晶硅膜上形成与基板上的栅极绝缘膜相似的绝缘膜。

2. 发明授权

US07943478B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07943478B2
公开(公告)日：2011-05-17
申请号：US12541457
申请日：2009-08-14
申请人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
发明人： Haruhiko Koyama , Mitsuhiro Noguchi , Minori Kajimoto
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/942 , Y10S438/975
摘要： In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.
摘要翻译：在半导体器件制造方法中，包括半导体层的衬底结构的表面被包括第一和第二开口的第一膜覆盖。第一开口被配置为对准标记。第二开口被构造为用于将杂质引入半导体层的第一预定位置的开口。在该方法中，使用与用作对准标记的第一开口对准的光掩模，在第一膜中形成第三开口。第三开口被构造为用于将杂质引入半导体层的第二预定位置的开口。

3. 发明授权

US07936093B2 Phase control switching device 有权
标题翻译：相控开关装置
公开(公告)号：US07936093B2
公开(公告)日：2011-05-03
申请号：US12515495
申请日：2007-02-15
申请人： Sadayuki Kinoshita , Kenji Kamei , Haruhiko Koyama , Tomohito Mori
发明人： Sadayuki Kinoshita , Kenji Kamei , Haruhiko Koyama , Tomohito Mori
IPC分类号： H01H47/00
CPC分类号： H01H9/563 , Y10T307/766 , Y10T307/826 , Y10T307/839
摘要： In a phase control switching device that controls a closing phase of a three-phase switching device connected between a power-supply-side transmission line and a compensation transmission line having a shunt reactor, a closing-phase control unit operates based on a closing command to the three-phase switching device, generates, for each phase, a closing phase in which the three-phase switching device is closed at zero points, both polarities of which are inverted into the same polarity, among zero points where zero points of a voltage changing ratio and zero points of the shunt reactor current coincide with each other, and controls the three-phase switching device.
摘要翻译：在控制连接在电源侧传输线和具有并联电抗器的补偿传输线之间的三相开关装置的闭合相位的相位控制开关装置中，闭合相位控制单元基于闭合指令对于三相开关装置，对于每个相位，在零点上将三相开关装置闭合的闭合相位（其两个极性被反转成相同的极性），在零点中产生零点，其中零点并联电抗器电流的电压变化率和零点相互重合，控制三相开关装置。

4. 发明申请

US20100085668A1 PHASE-CONTROL SWITCHING APPARATUS AND SWITCHING CONTROL METHOD FOR PHASE-CONTROL SWITCHING APPARATUS 有权
标题翻译：相位控制切换装置的相位控制切换控制方法
公开(公告)号：US20100085668A1
公开(公告)日：2010-04-08
申请号：US12527230
申请日：2007-04-20
申请人： Sadayuki Kinoshita , Kenji Kamei , Haruhiko Koyama , Tomohito Mori
发明人： Sadayuki Kinoshita , Kenji Kamei , Haruhiko Koyama , Tomohito Mori
IPC分类号： H02H7/04
CPC分类号： H02H9/002 , H01H9/56 , H02H7/04
摘要： A residual-magnetic-flux calculating unit includes a voltage-change-rate detecting unit that detects a transformer-voltage change rate from a phase voltage between a breaker and a transformer, a residual-magnetic-flux detecting unit that detects a residual magnetic flux remaining on the transformer based on the phase voltage, and a breaker-switching-state identifying unit that detects a switching state of the breaker. The residual-magnetic-flux calculating unit recalculates the residual magnetic flux based on the transformer-voltage change rate and a predetermined threshold while the breaker is in an open state.
摘要翻译：剩余磁通量计算单元包括电压变化率检测单元，其从断路器和变压器之间的相电压检测变压器电压变化率，剩余磁通量检测单元检测残余磁通量基于相电压保持在变压器上，以及断路器切换状态识别单元，其检测断路器的开关状态。剩余磁通计算单元在断路器处于打开状态的同时基于变压器电压变化率和预定阈值重新计算剩余磁通量。

5. 发明授权

US06897502B2 Semiconductor memory device and its manufacturing method 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06897502B2
公开(公告)日：2005-05-24
申请号：US10620698
申请日：2003-07-17
申请人： Shinichi Watanabe , Toyota Morimoto , Tohru Ozaki , Haruhiko Koyama
发明人： Shinichi Watanabe , Toyota Morimoto , Tohru Ozaki , Haruhiko Koyama
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A first impurity diffusion area is formed in the semiconductor substrate at a bottom of the first trench formed in a surface of the semiconductor substrate. A second impurity diffusion area is formed in the surface of the semiconductor substrate, each have one end contacting a first side wall of the first trench, and each have the same conductive type as the first impurity diffusion area. A first gate electrode is provided on the first side wall between the first and second impurity diffusion areas with a gate insulating film interposed therebetween. A first ferroelectric film is provided on a first lower electrode, which is provided on the second impurity area. A first upper electrode is provided on the first ferroelectric film. A first interconnection layer is provided above the first upper electrode. A first contact plug electrically connects the first interconnection layer and first impurity diffusion area.
摘要翻译：在形成于半导体衬底的表面中的第一沟槽的底部的半导体衬底中形成第一杂质扩散区。在半导体基板的表面形成第二杂质扩散区域，每个第一杂质扩散区域的一端与第一沟槽的第一侧壁接触，并且各自具有与第一杂质扩散区域相同的导电类型。第一栅电极设置在第一和第二杂质扩散区之间的第一侧壁上，其间插入有栅极绝缘膜。第一铁电体膜设置在设置在第二杂质区域上的第一下部电极上。第一上电极设置在第一铁电体膜上。第一互连层设置在第一上电极上方。第一接触插塞电连接第一互连层和第一杂质扩散区。

6. 发明授权

US07787228B2 Switchgear control apparatus 有权
标题翻译：开关柜控制装置
公开(公告)号：US07787228B2
公开(公告)日：2010-08-31
申请号：US11873076
申请日：2007-10-16
申请人： Haruhiko Koyama , Tomohito Mori , Kenji Kamei , Sadayuki Kinoshita
发明人： Haruhiko Koyama , Tomohito Mori , Kenji Kamei , Sadayuki Kinoshita
IPC分类号： H02H7/00
CPC分类号： H01H9/563 , H02P13/00
摘要： A switchgear control apparatus includes main contacts for first to third phases, operating mechanisms for activating the main contacts for the respective phases, voltage sensors for detecting phase voltages of a three-phase power source, and a contact closing control circuit. The contact closing control circuit first outputs a contact closing signal to the first-phase operating mechanism to close the first-phase main contact corresponding to a central leg of a core of a three-phase reactor at a first-phase voltage peak, and then a contact closing signal to the second- and third-phase operating mechanisms to simultaneously close the second- and third-phase main contacts corresponding to two outer legs of the reactor core at a zero-voltage point of the first phase three-quarter cycle later than close of the main contact for the first phase.
摘要翻译：开关控制装置包括用于第一至第三相的主触点，用于激活各相的主触头的操作机构，用于检测三相电源的相电压的电压传感器和触点闭合控制电路。接触闭合控制电路首先向第一相操作机构输出接点闭合信号，以将第一相电压峰值的三相电抗器的铁芯的中心支路对应的第一相主触点闭合，然后接触关闭信号到第二和第三相操作机构，以在第一阶段的四个周期的零电压点同时闭合对应于反应堆堆芯的两个外部柱的第二和第三相主触头比第一阶段的主要联系人接近。

7. 发明申请

US20100072828A1 PHASE CONTROL SWITCHING DEVICE 有权
标题翻译：相控开关装置
公开(公告)号：US20100072828A1
公开(公告)日：2010-03-25
申请号：US12515495
申请日：2007-02-15
申请人： Sadayuki Kinoshita , Kenji Kamei , Haruhiko Koyama , Tomohito Mori
发明人： Sadayuki Kinoshita , Kenji Kamei , Haruhiko Koyama , Tomohito Mori
IPC分类号： H01H47/00
CPC分类号： H01H9/563 , Y10T307/766 , Y10T307/826 , Y10T307/839
摘要： In a phase control switching device that controls a closing phase of a three-phase switching device connected between a power-supply-side transmission line and a compensation transmission line having a shunt reactor, a closing-phase control unit operates based on a closing command to the three-phase switching device, generates, for each phase, a closing phase in which the three-phase switching device is closed at zero points, both polarities of which are inverted into the same polarity, among zero points where zero points of a voltage changing ratio and zero points of the shunt reactor current coincide with each other, and controls the three-phase switching device.
摘要翻译：在控制连接在电源侧传输线和具有并联电抗器的补偿传输线之间的三相开关装置的闭合相位的相位控制开关装置中，闭合相位控制单元基于闭合指令对于三相开关装置，对于每个相位，在零点上将三相开关装置闭合的闭合相位（其两个极性被反转成相同的极性），在零点中产生零点，其中零点并联电抗器电流的电压变化率和零点相互重合，控制三相开关装置。

8. 发明授权

US07616419B2 Switchgear control apparatus 有权
标题翻译：开关柜控制装置
公开(公告)号：US07616419B2
公开(公告)日：2009-11-10
申请号：US11907054
申请日：2007-10-09
申请人： Haruhiko Koyama , Tomohito Mori , Kenji Kamei , Sadayuki Kinoshita
发明人： Haruhiko Koyama , Tomohito Mori , Kenji Kamei , Sadayuki Kinoshita
IPC分类号： H02H3/12
CPC分类号： H01H9/56 , H01H9/563
摘要： A switchgear control apparatus includes a zero point interval detecting circuit, an interruption time judgment circuit and a reclosing time decision circuit. The zero point interval detecting circuit detects time intervals between successive zero points of a main circuit current. The interruption time judgment circuit judges that interruption time of the main circuit current is time of a zero point immediately preceding a zero point at which a difference between the time interval between two successive zero points and half the period of a commercial AC voltage exceeds a specific value. Upon detecting the gradient of the main circuit current at the interruption time, the reclosing time decision circuit sets reclosing time at a point in phase where the AC voltage has a maximum negative value if the gradient is positive, and at a point in phase where the AC voltage has a maximum positive value if the gradient is negative.
摘要翻译：一种开关设备控制装置，包括零点间隔检测电路，中断时间判断电路和重合闸时间判定电路。零点间隔检测电路检测主电路电流的连续零点之间的时间间隔。中断时间判断电路判断主电路电流的中断时间是紧邻零点之间的零点的时间，在该零点之间，两个连续的零点之间的时间间隔与商用交流电压的一半的时间间隔之间的差超过特定的值。在检测到中断时的主电路电流的梯度时，重合闸时间决定电路将梯形为正的交流电压为最大负值的同相位置的重新闭合时间设定在同相位置如果梯度为负，则交流电压具有最大正值。

9. 发明授权

US08502298B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08502298B2
公开(公告)日：2013-08-06
申请号：US13053849
申请日：2011-03-22
申请人： Haruhiko Koyama
发明人： Haruhiko Koyama
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/0738 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L28/20
摘要： In one embodiment, a semiconductor device includes a resistor element and a stacked-gate type memory cell transistor. The resistor element includes a first conductive layer which is formed on a second conductive layer via a first insulating layer, and is electrically connected to an interconnect, the second conductive layer being on a substrate and in a floating state. The stacked-gate type memory cell transistor is on the substrate, and includes a floating gate formed of the same material as the second conductive layer.
摘要翻译：在一个实施例中，半导体器件包括电阻元件和堆叠栅型存储单元晶体管。电阻元件包括第一导电层，其经由第一绝缘层形成在第二导电层上，并且电连接到互连，第二导电层位于衬底上并处于浮置状态。叠层栅型存储单元晶体管在衬底上，并且包括由与第二导电层相同的材料形成的浮栅。

10. 发明授权

US08189360B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08189360B2
公开(公告)日：2012-05-29
申请号：US12725640
申请日：2010-03-17
申请人： Haruhiko Koyama
发明人： Haruhiko Koyama
IPC分类号： G11C5/02 , G11C5/06 , G11C16/04 , H01L29/788
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C16/04 , H01L27/11519 , H01L27/11521
摘要： A semiconductor memory device includes first and second element regions having a rectangular bent portion and a pair of straight line portions connected to both ends of the bent portions, respectively. The pair of straight line portions extends in an opposite direction each other along a first direction. A first element region is arranged in parallel with the second element region so that the first and second element regions are isolated by an element isolation region, and the first and second bent portions are arranged along a second direction in which the first direction intersects with the second direction at an acute angle. A select gate line connected to select transistors extends in the second direction. A plurality of word lines connected to the memory cells are arranged in parallel with the select gate line in an opposite side of the bent portions with respect to the select gate line.
摘要翻译：半导体存储器件包括分别具有矩形弯曲部分和连接到弯曲部分两端的一对直线部分的第一和第二元件区域。一对直线部沿着第一方向彼此相反的方向延伸。第一元件区域与第二元件区域平行地布置，使得第一和第二元件区域被元件隔离区域隔离，并且第一和第二弯曲部分沿着第一方向与第一元件区域相交的第二方向第二方向为锐角。连接到选择晶体管的选择栅极线沿第二方向延伸。连接到存储器单元的多个字线相对于选择栅极线在弯曲部分的相对侧与选择栅极线平行布置。

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