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    • 2. 发明授权
    • Video coding apparatus and decoding apparatus
    • 视频编码装置和解码装置
    • US06333949B1
    • 2001-12-25
    • US09474133
    • 1999-12-29
    • Akira NakagawaKimihiko KazuiEishi MorimatsuTakahiro Shimizu
    • Akira NakagawaKimihiko KazuiEishi MorimatsuTakahiro Shimizu
    • H04N736
    • H04N19/59H04N19/105H04N19/117H04N19/134H04N19/139H04N19/152H04N19/159H04N19/176H04N19/196H04N19/527H04N19/61H04N19/82H04N19/86
    • Video coding apparatus and decoding apparatus capable of reproducing decoded pictures without introducing unwanted noises, even if any considerable difference in pixel values or discontinuity exists at a certain block boundary. In a video coding apparatus employing predictive techniques, a dequantizer and an inverse DCT processor reproduce a prediction error signal from quantized transform coefficients. Here, a first resolution conversion unit (or downsampling unit) might have subsampled the original prediction error signal to reduce its picture resolution. If this is the case, a second resolution conversion unit (or upsampling unit) attempts to restore the original resolution of the prediction error signal by applying an upsampling process to the reproduced prediction error signal having the reduced resolution. In this upsampling process, each new pixel value in a certain block are calculated with reference to some surrounding pixels. The upsampling process, however, will not refer to the pixels belonging to any adjacent blocks that are subject to another coding scheme which is different from the coding scheme of the present block of interest. As an alternate arrangement, the upsampling process will entirely neglect the pixels in any other blocks but will refer only to the present block, block-by-block basis, comprising the substep of (b1) performing an upsampling process of each block with the low resolution to regain the high resolution, while not referring, when calculating a pixel value in a block that is subject to one of the coding schemes, to any pixels that belong to any other block adjacent to the block of interest if the adjacent block is subject to the other coding scheme, but referring at least to the pixels belonging to the block of interest.
    • 即使在某个块边界处存在像素值或不连续性的任何相当大的差异,也能够再现解码图像而不引入不需要的噪声的视频编码装置和解码装置。 在采用预测技术的视频编码装置中,去量化器和逆DCT处理器从量化变换系数再现预测误差信号。 这里,第一分辨率转换单元(或下采样单元)可以对原始预测误差信号进行二次采样以降低其图像分辨率。 如果是这种情况,则第二分辨率转换单元(或上采样单元)尝试通过对具有降低的分辨率的再现的预测误差信号应用上采样处理来恢复预测误差信号的原始分辨率。 在该上采样处理中,参考一些周围像素计算某个块中的每个新像素值。 然而,上采样处理将不涉及属于与当前感兴趣块的编码方案不同的另一编码方案的属于任何相邻块的像素。 作为替代布置,上采样处理将完全忽略任何其他块中的像素,但将逐块地参考当前块,包括(b1)的子步骤,以低的速率执行每个块的上采样处理 分辨率重新获得高分辨率,而当计算受到编码方案之一的块中的像素值而不指向属于与感兴趣块相邻的任何其他块的任何像素时,如果相邻块为对象 至少涉及属于感兴趣块的像素。
    • 4. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08363468B2
    • 2013-01-29
    • US13033309
    • 2011-02-23
    • Takahiro ShimizuNoboru Shibata
    • Takahiro ShimizuNoboru Shibata
    • G11C11/34
    • G11C16/12G11C11/5628G11C16/0483G11C2211/5641G11C2211/5643
    • A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.
    • 本发明的半导体存储器件包括存储单元阵列,该存储单元阵列包括具有多个存储单元的第一区域,每个存储器单元能够存储n位数据(n为自然数)和具有多个存储单元的第二区域 每个能够存储k比特数据(k> n:k是自然数),包括多个数据高速缓存的数据存储电路,以及控制该存储单元阵列和数据存储电路的控制电路 将从第一区域中的k / n个存储单元读取的k位数据存储到数据存储电路中的方式,并将k位数据存储到第二区域中的存储单元中。
    • 7. 发明授权
    • Centrifuge having pivotally supported door
    • 离心机枢轴支撑门
    • US07815560B2
    • 2010-10-19
    • US11525835
    • 2006-09-25
    • Hiroshi HayasakaTakahiro ShimizuYuki Shimizu
    • Hiroshi HayasakaTakahiro ShimizuYuki Shimizu
    • B04B7/02
    • B04B7/02
    • A centrifuge includes a frame, a door, a restricting part, a first spring member, and a second spring member. The frame has an opening on top thereof, when the frame is disposed in an orientation in which the frame is intended to be placed. The door is movably supported on the frame to be capable of opening and closing the opening. The restricting part is provided on the frame and defines a prescribed region. The first spring member has one end pivotally supported on the door, and another end pivotally supported on the frame. The second spring member has one end pivotally supported on the door, and another end that is movable within the prescribed region.
    • 离心机包括框架,门,限制部分,第一弹簧部件和第二弹簧部件。 当框架设置在框架旨在放置的方向上时,框架在其顶部具有开口。 门可移动地支撑在框架上以能够打开和关闭开口。 限制部分设置在框架上并限定规定的区域。 第一弹簧构件的一端枢转地支撑在门上,另一端枢转地支撑在框架上。 第二弹簧构件的一端枢转地支撑在门上,另一端可在规定区域内移动。
    • 8. 发明申请
    • Centrifuge
    • 离心机
    • US20070072759A1
    • 2007-03-29
    • US11525835
    • 2006-09-25
    • Hiroshi HayasakaTakahiro ShimizuYuki Shimizu
    • Hiroshi HayasakaTakahiro ShimizuYuki Shimizu
    • B04B7/02
    • B04B7/02
    • A centrifuge includes a frame, a door, a restricting part, a first spring member, and a second spring member. The frame has an opening on top thereof, when the frame is disposed in an orientation in which the frame is intended to be placed. The door is movably supported on the frame to be capable of opening and closing the opening. The restricting part is provided on the frame and defines the prescribed region. The first spring member has one end pivotally supported on the door, and another end pivotally supported on the frame. The second spring member has one end pivotally supported on the door, and another end that is movable within a prescribed region.
    • 离心机包括框架,门,限制部分,第一弹簧部件和第二弹簧部件。 当框架设置在框架旨在放置的方向上时,框架在其顶部具有开口。 门可移动地支撑在框架上以能够打开和关闭开口。 限制部分设置在框架上并限定规定的区域。 第一弹簧构件的一端枢转地支撑在门上,另一端枢转地支撑在框架上。 第二弹簧构件的一端枢转地支撑在门上,另一端可在规定区域内移动。
    • 9. 发明授权
    • Semiconductor memory system with current consumption control
    • 半导体存储器系统具有电流消耗控制
    • US09244870B2
    • 2016-01-26
    • US13426977
    • 2012-03-22
    • Takahiro Shimizu
    • Takahiro Shimizu
    • G06F13/16
    • G06F13/1689
    • According to one embodiment, a semiconductor memory system includes semiconductor memories, and a memory controller configured to control the semiconductor memories. Each of the semiconductor memories is configured to execute an internal sequence including operations and have a wait period after an end of each of the operations, to notify, during the wait period, a status signal, which notifies in advance a start of a next operation, to the memory controller, and to start the next operation upon receiving a restart instruction of the internal sequence from the memory controller.
    • 根据一个实施例,半导体存储器系统包括半导体存储器和被配置为控制半导体存储器的存储器控​​制器。 每个半导体存储器被配置为执行包括操作的内部序列,并且在每个操作结束之后具有等待周期,以在等待期间通知状态信号,其预先通知下一个操作的开始 ,并且在从存储器控制器接收到内部序列的重新启动指令时开始下一个操作。
    • 10. 发明授权
    • Communication apparatus, reception control method, and transmission control method
    • 通信装置,接收控制方法和传输控制方法
    • US09071582B2
    • 2015-06-30
    • US13611618
    • 2012-09-12
    • Takahiro Shimizu
    • Takahiro Shimizu
    • H04L29/06G06F12/14
    • H04L63/0485H04L63/164H04L69/22
    • Lookaside-type communication apparatus and reception and transmission control methods make high-rate communication of a packet including encrypted data. Receive data including encrypted data are supplied to an encryption data processing part, and supplied to a security part through a second bus when the packet is received. The encrypted data becomes plain-text data in the security part, and supplied to the control part through the system bus. Transmit data including a data body including a plain-text data to be encrypted are supplied to the security part when the packet is transmitted. The plain-text data become the encrypted data in the security part, and the transmit data having the data body including the encrypted data are supplied to the encryption data processing part through the second bus. The transmit data are transmitted in the form of the packet in the transmission and reception part.
    • 后备式通信装置和接收和发送控制方法使得包括加密数据的分组的高速率通信。 包含加密数据的接收数据被提供给加密数据处理部分,并且当接收到分组时通过第二总线提供给安全部分。 加密数据成为安全部分中的明文数据,并通过系统总线提供给控制部分。 当发送分组时,将包括要加密的明文数据的数据主体的发送数据提供给安全部分。 明文数据成为安全部分中的加密数据,具有加密数据的数据体的发送数据通过第二总线提供给加密数据处理部。 发送数据在发送和接收部分中以分组的形式发送。