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1. 发明授权

US5654923A Semiconductor data storage apparatus 失效
标题翻译：半导体数据存储装置
公开(公告)号：US5654923A
公开(公告)日：1997-08-05
申请号：US668811
申请日：1996-06-24
申请人： Akira Mizobata , Masanori Nagahama , Tadakatu Watanabe
发明人： Akira Mizobata , Masanori Nagahama , Tadakatu Watanabe
IPC分类号： G11C17/00 , G06K19/07 , G11C16/02 , G11C16/06
CPC分类号： G11C16/10 , G11C16/32
摘要： A semiconductor data storage apparatus having a plurality of memory devices which are switched to a predetermined mode when a software command has been written, which have waiting time during execution of the command after the command has been written and from which data can be collectively erased, the semiconductor data storage apparatus being arranged to shorten the time required to erase data. A memory device is activated in response to a memory selection signal supplied by a decoder, a write enable signal, which has been, by an AND gate circuit, selectively supplied in response to the selection signal, brings the memory device into a write mode, upper address signals are sequentially switched during waiting time during execution of erasure after an erase command has been written so as to sequentially write erase commands on next memory devices by the decoder and AND gate circuits.
摘要翻译：一种具有多个存储器件的半导体数据存储装置，当已经写入已经写入了命令的命令执行中的等待时间，并且可以从哪个数据被共同地擦除时，已经写入了已经写入了软件命令的预定模式的存储器件，半导体数据存储装置被布置为缩短擦除数据所需的时间。响应于由解码器提供的存储器选择信号激活存储器件，由与门电路一起被响应于选择信号有选择地提供的写使能信号使存储器件进入写模式，在写入擦除命令之后的擦除执行期间的等待时间期间，顺序地切换高地址信号，以便由解码器和与门电路在下一个存储器件上顺序写入擦除命令。

2. 发明授权

US5559738A Semiconductor data storage apparatus 失效
标题翻译：半导体数据存储装置
公开(公告)号：US5559738A
公开(公告)日：1996-09-24
申请号：US361723
申请日：1994-12-22
申请人： Akira Mizobata , Masanori Nagahama , Tadakatu Watanabe
发明人： Akira Mizobata , Masanori Nagahama , Tadakatu Watanabe
IPC分类号： G11C17/00 , G06K19/07 , G11C16/02 , G11C16/06
CPC分类号： G11C16/10 , G11C16/32
摘要： A semiconductor data storage apparatus having a plurality of memory devices which are switched to a predetermined mode when a software command has been written, which have waiting time during execution of the command after the command has been written and from which data can be collectively erased, the semiconductor data storage apparatus being arranged to shorten the time required to erase data. A memory device is activated in response to a memory selection signal supplied by a decoder, a write enable signal, which has been, by an AND gate circuit, selectively supplied in response to the selection signal, brings the memory device into a write mode, upper address signals are sequentially switched during a waiting time during execution of erasure after an erase command has been written so as to sequentially write erase commands on next memory devices by the decoder and AND gate circuits.
摘要翻译：一种具有多个存储器件的半导体数据存储装置，当已经写入已经写入了命令的命令执行中的等待时间，并且可以从哪个数据被共同地擦除时，已经写入了已经写入了软件命令的预定模式的存储器件，半导体数据存储装置被布置为缩短擦除数据所需的时间。响应于由解码器提供的存储器选择信号激活存储器件，由与门电路一起被响应于选择信号有选择地提供的写使能信号使存储器件进入写模式，在写入擦除命令之后的擦除执行期间的等待时间期间，顺序地切换高地址信号，以便由解码器和与门电路在下一个存储器件上顺序写入擦除命令。

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