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1. 发明申请

US20060140253A1 Ultra-wideband transmitter and transceiver using the same 审中-公开
标题翻译：超宽带发射机和收发器使用相同
公开(公告)号：US20060140253A1
公开(公告)日：2006-06-29
申请号：US11316729
申请日：2005-12-27
申请人： Akira Maeki , Ryosuke Fujiwara , Masaaki Shida , Masaru Kokubo , Takayasu Norimatsu
发明人： Akira Maeki , Ryosuke Fujiwara , Masaaki Shida , Masaru Kokubo , Takayasu Norimatsu
IPC分类号： H04B1/707 , H04B1/69
CPC分类号： H04B1/7174
摘要： An ultra-wideband transmitter is provided which can reduce a leak of a local signal into a transmitted signal with a pulse train output from an antenna in UWB-IR communication. The transmitter comprises a pulse generator 0140 for generating a pulse signal having a pulse train of pulses produced intermittently according to data to be transmitted, an oscillator 0120 for producing a local signal, a frequency converter 0130 to which the pulse signal output from the pulse generator and the local signal output from the oscillator are input, and for frequency-converting the pulse signal to output a RF signal, an amplifier 0110 for amplifying the RF signal output from the frequency converter, and an antenna 0000 for emitting the RF signal output from the amplifier in the air. In a period corresponding to a pause period of the pulses produced intermittently, a leak of the local signal into the RF signal output from the antenna is reduced using a control signal 0300.
摘要翻译：提供了一种超宽带发射器，其可以通过在UWB-IR通信中从天线输出的脉冲串来减少本地信号泄漏到发射信号中。发射机包括脉冲发生器0140，用于根据要发射的数据产生具有间歇产生的脉冲脉冲串的脉冲信号;振荡器0120，用于产生本地信号;频率转换器0130，从脉冲发生器输出的脉冲信号并输入从振荡器输出的本地信号，为了对脉冲信号进行频率转换以输出RF信号，放大器0110用于放大从频率转换器输出的RF信号，以及用于发射RF信号的天线0000 放大器在空气中。在对应于间歇产生的脉冲的暂停时段的时间段内，使用控制信号0300，将本地信号的泄漏从天线输出的RF信号中减少。

2. 发明申请

US20060197618A1 Pulse generator and the transmitter with a pulse generator 有权
标题翻译：脉冲发生器和带脉冲发生器的变送器
公开(公告)号：US20060197618A1
公开(公告)日：2006-09-07
申请号：US11334573
申请日：2006-01-19
申请人： Takayasu Norimatsu , Ryosuke Fujiwara , Masaru Kokubo , Akira Maeki
发明人： Takayasu Norimatsu , Ryosuke Fujiwara , Masaru Kokubo , Akira Maeki
IPC分类号： H03B29/00
CPC分类号： H04B1/7174 , H04L25/03834
摘要： The object is simplification of a configuration in a pulse generator for UWB transmission, lower power consumption, and suppression of LO leakage by nonuse of the LO signal. A pulse generator comprises: a clock generator (CLK) for giving clock of a predetermined period; a delay circuit (DLY) equipped with a function of controlling a delay time and for delaying the clock; a square-wave pulse generation circuit (SWPG), by receiving information being spread by a spread code, modulates phases of square wave pulses that have a pulse width corresponding to a differential delay for one stage of the delay circuit by comparing the signals outputted from the delay circuit and having different delay times, and outputs the square wave pulses; and an amplitude control unit (AMPC) that outputs an impulse sequence having the pulse width of the square wave in a predetermined amplitude by receiving a square wave pulse sequence outputted from the square-wave pulse generation circuit at different timings, and combines the impulses; and outputs pulses that have a predetermined envelope form.
摘要翻译：目的是简化用于UWB传输的脉冲发生器中的配置，降低功耗，并且通过不使用LO信号来抑制LO泄漏。脉冲发生器包括：用于给定预定周期的时钟的时钟发生器（CLK）; 具有控制延迟时间和延迟时钟的功能的延迟电路（DLY）; 方波脉冲发生电路（SWPG）通过接收由扩展码进行扩展的信息，通过比较输出的信号来调制具有对应于延迟电路的一级的差分延迟的脉冲宽度的方波脉冲的相位延迟电路并具有不同的延迟时间，并输出方波脉冲; 以及振幅控制单元（AMPC），通过在不同的定时接收从方波脉冲发生电路输出的方波脉冲序列，输出具有预定振幅的方波脉冲宽度的脉冲序列，并组合脉冲; 并输出具有预定包络形式的脉冲。

3. 发明授权

US07664161B2 Pulse generator and the transmitter with a pulse generator 有权
标题翻译：脉冲发生器和带脉冲发生器的变送器
公开(公告)号：US07664161B2
公开(公告)日：2010-02-16
申请号：US11334573
申请日：2006-01-19
申请人： Takayasu Norimatsu , Ryosuke Fujiwara , Masaru Kokubo , Akira Maeki
发明人： Takayasu Norimatsu , Ryosuke Fujiwara , Masaru Kokubo , Akira Maeki
IPC分类号： H04B1/00
CPC分类号： H04B1/7174 , H04L25/03834
摘要： A pulse generator for UWB transmission, lower power consumption, and suppression of LO leakage by nonuse of the LO signal. The pulse generator includes a clock generator (CLK) for giving clock of a predetermined period; a delay circuit (DLY) equipped with a function of controlling a delay time and for delaying the clock; a square-wave pulse generation circuit (SWPG) that receives information being spread by a spread code and modulates phases of square wave pulses that have a pulse width corresponding to a differential delay for one stage of the delay circuit; and an amplitude control unit (AMPC) that outputs an impulse sequence having the pulse width of the square wave in a predetermined amplitude and combines the impulses; and outputs pulses that have a predetermined envelope form.
摘要翻译：用于UWB传输的脉冲发生器，较低的功耗，并且通过不使用LO信号来抑制LO泄漏。脉冲发生器包括用于给定预定周期的时钟的时钟发生器（CLK）; 具有控制延迟时间和延迟时钟的功能的延迟电路（DLY）; 接收由扩展码扩展的信息的方波脉冲发生电路（SWPG），并且对延迟电路的一级具有对应于差分延迟的脉冲宽度的方波脉冲的相位进行调制; 以及幅度控制单元（AMPC），其以预定的幅度输出具有所述方波的脉冲宽度的脉冲序列并组合所述脉冲; 并输出具有预定包络形式的脉冲。

4. 发明授权

US08299865B2 Quadrature modulator and semiconductor integrated circuit with it built-in 失效
标题翻译：正交调制器和半导体集成电路内置
公开(公告)号：US08299865B2
公开(公告)日：2012-10-30
申请号：US12942533
申请日：2010-11-09
申请人： Takahiro Nakamura , Taizo Yamawaki , Takayasu Norimatsu , Takao Kihara
发明人： Takahiro Nakamura , Taizo Yamawaki , Takayasu Norimatsu , Takao Kihara
IPC分类号： H04L27/20 , H03C3/40
CPC分类号： H04L27/36
摘要： A quadrature modulator has first to fourth transistors, a first node, a second node, and a first output node. A non-inversion in-phase analog signal, an inversion in-phase analog signal, a non-inversion quadrature analog signal, and an inversion quadrature analog signal are supplied to input electrodes of the first to fourth transistors, respectively. Control electrodes of the first to fourth transistors respond to a non-inversion in-phase RF signal, an inversion in-phase RF signal, a non-inversion quadrature RF signal, and an inversion quadrature RF signal, respectively. Output electrodes of the first and second transistors are coupled to the first node, and output electrodes of the third and fourth transistors are coupled to the second node. A first high-pass filter is coupled between the first node and the first output node, and a second high-pass filter is coupled between the second node and the first output node.
摘要翻译：正交调制器具有第一至第四晶体管，第一节点，第二节点和第一输出节点。分别向第一至第四晶体管的输入电极提供非反相同相模拟信号，反相同相模拟信号，非反相正交模拟信号和反相正交模拟信号。第一至第四晶体管的控制电极分别响应非反相同相RF信号，反相同相RF信号，非反相正交RF信号和反相正交RF信号。第一和第二晶体管的输出电极耦合到第一节点，并且第三和第四晶体管的输出电极耦合到第二节点。第一高通滤波器耦合在第一节点和第一输出节点之间，并且第二高通滤波器耦合在第二节点和第一输出节点之间。

5. 发明申请

US20100052795A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20100052795A1
公开(公告)日：2010-03-04
申请号：US12540248
申请日：2009-08-12
申请人： Takahiro Nakamura , Tomomitsu Kitamura , Taizo Yamawaki , Takayasu Norimatsu , Toshiya Uozumi
发明人： Takahiro Nakamura , Tomomitsu Kitamura , Taizo Yamawaki , Takayasu Norimatsu , Toshiya Uozumi
IPC分类号： H03L7/099
CPC分类号： H03J3/20 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B5/1293 , H03J2200/10
摘要： The present invention provides a semiconductor integrated circuit capable of reducing a chip occupied area and reducing variations in control gain of a digitally controlled oscillator. The semiconductor integrated circuit is equipped with the digitally controlled oscillator. The digitally controlled oscillator comprises oscillation transistors and a resonant circuit. The resonant circuit comprises inductances, a frequency coarse-tuning variable capacitor array and a frequency fine-tuning variable capacitor array. The frequency coarse-tuning variable capacitor array comprises a plurality of coarse-tuning capacitor unit cells. The frequency fine-tuning variable capacitor array comprises a plurality of fine-tuning capacitor unit cells. The capacitance values of the coarse-tuning capacitor unit cells of the frequency coarse-tuning variable capacitor array are set in accordance with a binary weight 2M−1. The capacitance values of the fine-tuning capacitor unit cells of the frequency fine-tuning variable capacitor array are also set in accordance with a binary weight 2N−1.
摘要翻译：本发明提供一种能够减少芯片占用面积并减少数字控制振荡器的控制增益的变化的半导体集成电路。半导体集成电路配有数字控制振荡器。数字控制振荡器包括振荡晶体管和谐振电路。谐振电路包括电感，频率粗调可变电容器阵列和频率微调可变电容器阵列。频率粗调可变电容器阵列包括多个粗调谐电容器单元。频率微调可变电容器阵列包括多个微调电容器单元。频率粗调可变电容器阵列的粗调电容器单元的电容值根据二进制权重2M-1来设定。频率微调可变电容器阵列的微调电容器单元的电容值也根据二进制权重2N-1设定。

6. 发明授权

US08442461B2 Transmitter and semiconductor integrated circuit available for it 有权
标题翻译：发射机和半导体集成电路可用
公开(公告)号：US08442461B2
公开(公告)日：2013-05-14
申请号：US12854216
申请日：2010-08-11
申请人： Takayasu Norimatsu , Taizo Yamawaki , Yukinori Akamine , Koji Maeda
发明人： Takayasu Norimatsu , Taizo Yamawaki , Yukinori Akamine , Koji Maeda
IPC分类号： H03C1/62 , H04B17/00
CPC分类号： H04B1/0483 , H03C5/00 , H04B2001/0491
摘要： The transmitter synthesizes amplitude and phase components and calibrates a delay mismatch between amplitude and phase components with high accuracy at high speed. The transmitter has: a digital-to-analog converter (DAC) and a low-pass filter (LPF) in its amplitude-signal path; and a phase modulator operable to convert up a phase component into an RF component in its phase-signal path. In an operation of delay calibration, a test input signal is supplied to a delay-calibrating unit in the amplitude-signal path, and the delay-calibrating unit provides a test input signal to DAC. Then, LPF generates a test output signal. The delay-calibrating unit detects a delay of the test output signal relative to the test input signal, calibrates an amplitude signal delay in a range from the input of the delay-calibrating unit to the output of LPF, reduces the difference between amplitude and phase signal delays of the phase modulator in the phase-signal path.
摘要翻译：发射机合成幅度和相位分量，并以高精度高速校准振幅和相位分量之间的延迟失配。发射机具有：幅度信号路径中的数模转换器（DAC）和低通滤波器（LPF）; 以及相位调制器，其可操作以将相位分量转换成其相位信号路径中的RF分量。在延迟校准的操作中，将测试输入信号提供给幅度信号路径中的延迟校准单元，并且延迟校准单元向DAC提供测试输入信号。然后，LPF产生测试输出信号。延迟校准单元检测测试输出信号相对于测试输入信号的延迟，校准从延迟校准单元的输入到LPF的输出的范围内的幅度信号延迟，减小幅度和相位之间的差异相位调制器在相位信号路径中的信号延迟。

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